1/* $NetBSD: virtex_start.S,v 1.9 2018/07/15 05:16:42 maxv Exp $ */ 2 3/* 4 * Copyright (c) 2006 Jachym Holecek 5 * All rights reserved. 6 * 7 * Written for DFC Design, s.r.o. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32/* 33 * This file is based on startup code of Walnut and Explora boards. 34 */ 35 36#include "opt_ddb.h" 37#include "opt_lockdebug.h" 38#include "opt_modular.h" 39#include "opt_multiprocessor.h" 40#include "opt_ppcarch.h" 41#include "opt_ppcparam.h" 42#include "opt_virtex.h" 43#include "assym.h" 44#include "ksyms.h" 45 46#include <sys/syscall.h> 47 48#include <machine/param.h> 49#include <machine/psl.h> 50#include <machine/trap.h> 51#include <machine/asm.h> 52 53#include <powerpc/spr.h> 54#include <powerpc/ibm4xx/spr.h> 55#include <powerpc/ibm4xx/dcr4xx.h> 56 57 58/* N megabytes. */ 59#define MB(n) ((n)*1024*1024) 60 61/* Set bit (beginning with MSB) for each 128MB of RAM. */ 62#define PHYSMEM_REGIONS_MASK ~((1 << (32 - MB(PHYSMEM)/MB(128))) - 1) 63 64/* For kvm_mkdb, supposed to mark the start of kernel text. */ 65 .text 66 .globl _C_LABEL(kernel_text) 67_C_LABEL(kernel_text): 68 69/* Startup entry. This must be the first thing in the text segment! */ 70 .text 71 .globl __start 72__start: 73 /* Disable MMU/exceptions */ 74 lis %r0, 0 75 mtmsr %r0 76 77 /* Disable timers */ 78 lis %r0, 0 79 mttcr %r0 80 81 sync 82 isync 83 84 /* Disable caches */ 85 mtdccr %r0 86 mticcr %r0 87 sync 88 isync 89 90 /* Invalidate I$, operands ignored on the 405 */ 91 li %r0,0 /* just in case... */ 92 iccci %r0,%r0 93 94 /* Invalidate D$, hardcoded for 16KB size, 32B line */ 95 li %r7,256 /* # of congruence classes */ 96 mtctr %r7 97 li %r6,0 981: 99 dccci %r0,%r6 /* invalidates both ways */ 100 addi %r6,%r6,32 101 bdnz 1b 102 103 /* 104 * Errata 213: Incorrect data may be flushed from the data cache. 105 * Cores: PPC405D5X1, PPC405D5X2 106 * Workaround: #1, CCR0 modification sequence #2 107 * Note: Meaning of bits we need to set is undocumented. 108 */ 109 sync 110 mfccr0 %r0 111 oris %r0,%r0,0x50000000@h 112 mtccr0 %r0 113 isync 114 115 /* 116 * Errata 58: Load string instructions may write incorrect 117 * data into the last GPR targeted in operation. 118 * Cores: PPC405GP 119 * Workaround: set OCM0_DSCNTL[DSEN]=0 and OCM0_DSCNTL[DOF]=0 120 */ 121 mtdcr DCR_OCM0_DSCNTL,%r0 /* Disable Data access to OCM */ 122 123#if 0 124 /* Allow cacheing for whole RAM. */ 125 lis %r0,PHYSMEM_REGIONS_MASK@ha 126 ori %r0,%r0,PHYSMEM_REGIONS_MASK@l 127#else 128#ifndef PPC_4XX_NOCACHE 129 /* Allow cacheing for only the first 1GB of RAM */ 130 lis %r0,0xff00 131 mtdccr %r0 132 mticcr %r0 133#endif /* PPC_4XX_NOCACHE */ 134#endif 135 136 /* Invalidate all TLB entries */ 137 tlbia 138 sync 139 isync 140 141 /* Set kernel MMU context, we'll enable MMU in initppc() */ 142 li %r0,KERNEL_PID 143 mtpid %r0 144 sync 145 isync 146 147 /* Setup endkernel argument for initppc() and INIT_CPUINFO */ 148 lis %r4,_C_LABEL(end)@h 149 ori %r4,%r4,_C_LABEL(end)@l 150 151 /* Clear .bss segment */ 152 lis %r7,_C_LABEL(edata)-4@h 153 ori %r7,%r7,_C_LABEL(edata)-4@l 154 li %r3,0 1552: stwu %r3,4(%r7) 156 cmpw %r7,%r4 157 bne+ 2b 158 159#if NKSYMS || defined(DDB) || defined(MODULAR) 160 /* We don't have a symbol table, so set startsym = endsym = end */ 161 lis %r7,_C_LABEL(startsym)@ha 162 ori %r7,%r7,_C_LABEL(startsym)@l 163 stw %r4,0(%r7) 164 lis %r7,_C_LABEL(endsym)@ha 165 ori %r7,%r7,_C_LABEL(endsym)@l 166 stw %r4,0(%r7) 167#endif 168 169 /* INIT_CPUINFO will 'addi', so clean up. */ 170 lis %r1,0 171 172 INIT_CPUINFO(4,1,9,0) 173 174 /* startkernel argument for initppc */ 175 lis %r3,__start@h 176 addi %r3,%r3,__start@l 177 178 bl _C_LABEL(initppc) 179 bl _C_LABEL(main) 180 181loop: /* UNREACHED */ 182 b loop 183 184#include <powerpc/ibm4xx/4xx_locore.S> 185