1 /* 2 * Memory and machine-specific definitions. Used in C and assembler. 3 */ 4 #define KiB 1024u /* Kibi 0x0000000000000400 */ 5 #define MiB 1048576u /* Mebi 0x0000000000100000 */ 6 #define GiB 1073741824u /* Gibi 000000000040000000 */ 7 8 /* 9 * Not sure where these macros should go. 10 * This probably isn't right but will do for now. 11 * The macro names are problematic too. 12 */ 13 /* 14 * In BITN(o), 'o' is the bit offset in the register. 15 * For multi-bit fields use F(v, o, w) where 'v' is the value 16 * of the bit-field of width 'w' with LSb at bit offset 'o'. 17 */ 18 #define BITN(o) (1<<(o)) 19 #define F(v, o, w) (((v) & ((1<<(w))-1))<<(o)) 20 21 /* 22 * Sizes 23 */ 24 #define BY2PG (4*KiB) /* bytes per page */ 25 #define PGSHIFT 12 /* log(BY2PG) */ 26 27 #define MAXMACH 1 /* max # cpus system can run */ 28 #define MACHSIZE BY2PG 29 30 #define KSTKSIZE (8*KiB) 31 #define STACKALIGN(sp) ((sp) & ~3) /* bug: assure with alloc */ 32 33 /* 34 * Address spaces. 35 * KTZERO is used by kprof and dumpstack (if any). 36 * 37 * KZERO is mapped to physical 0. 38 * u-boot claims to take 0 - 8MB. 39 * 40 * vectors are at 0, plan9.ini is at KZERO+4K and is limited to 16K by 41 * devenv. L2 PTEs for trap vectors & i/o regs are stored from KZERO+56K 42 * to L1-MACHSIZE (KZERO+60K). cpu0's Mach struct is at L1 - MACHSIZE(4K) 43 * to L1 (KZERO+60K to KZERO+64K). L1 PTEs are stored from L1 to L1+32K 44 * (KZERO+64K to KZERO+96K). KTZERO may be anywhere after KZERO+96K. 45 */ 46 47 #define KSEG0 0x60000000 /* kernel segment */ 48 /* mask to check segment; good for 512MB dram */ 49 #define KSEGM 0xE0000000 50 #define KZERO KSEG0 /* kernel address space */ 51 #define CONFADDR (KZERO+4*KiB) /* unparsed plan9.ini */ 52 #define L1 (KZERO+64*KiB) /* tt ptes: 16KiB aligned */ 53 #define KTZERO (KZERO+0x800000) /* kernel text start */ 54 55 #define UZERO 0 /* user segment */ 56 #define UTZERO (UZERO+BY2PG) /* user text start */ 57 #define UTROUND(t) ROUNDUP((t), BY2PG) 58 #define USTKTOP KZERO /* user segment end +1 */ 59 #define USTKSIZE (8*1024*1024) /* user stack size */ 60 #define TSTKTOP (USTKTOP-USTKSIZE) /* sysexec temporary stack */ 61 #define TSTKSIZ 256 62 63 /* address at which to copy and execute rebootcode */ 64 #define REBOOTADDR KADDR(0x100) 65 66 /* 67 * Time. 68 * Does this need to be here? Used in assembler? 69 */ 70 #define HZ 100 /* clock frequency */ 71 #define MS2HZ (1000/HZ) /* millisec per clock tick */ 72 #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */ 73 74 /* 75 * More accurate time 76 */ 77 #define CLOCKFREQ (200*1000*1000) /* TCLK on sheeva: 200MHz */ 78 //#define MS2TMR(t) ((ulong)(((uvlong)(t)*CLOCKFREQ)/1000)) 79 //#define US2TMR(t) ((ulong)(((uvlong)(t)*CLOCKFREQ)/1000000)) 80 81 /* 82 * Legacy... 83 */ 84 #define BLOCKALIGN 32 /* only used in allocb.c */ 85 #define KSTACK KSTKSIZE 86 87 /* 88 * Sizes 89 */ 90 #define BI2BY 8 /* bits per byte */ 91 #define BY2SE 4 92 #define BY2WD 4 93 #define BY2V 8 /* only used in xalloc.c */ 94 95 #define CACHELINESZ 32 96 #define PTEMAPMEM (1024*1024) 97 #define PTEPERTAB (PTEMAPMEM/BY2PG) 98 #define SEGMAPSIZE 1984 99 #define SSEGMAPSIZE 16 100 #define PPN(x) ((x)&~(BY2PG-1)) 101 102 /* 103 * With a little work these move to port. 104 */ 105 #define PTEVALID (1<<0) 106 #define PTERONLY 0 107 #define PTEWRITE (1<<1) 108 #define PTEUNCACHED (1<<2) 109 #define PTEKERNEL (1<<3) 110 111 /* 112 * Physical machine information from here on. 113 */ 114 #define PHYSDRAM 0 115 116 /* from 0x80000000 up is uncached by L2 (see archkw.c) */ 117 #define PHYSCESASRAM 0xc8010000 118 #define PHYSNAND2 0xd8000000 /* guru */ 119 #define PHYSSPIFLASH 0xe8000000 /* optional spi flash (dream) */ 120 /* this address is configured by u-boot, and is 0xd0000000 at reset */ 121 #define PHYSIO 0xf1000000 /* internal registers */ 122 #define PHYSCONS (PHYSIO + 0x12000) /* uart */ 123 #define PHYSNAND1 0xf9000000 /* sheeva/openrd (remapped) */ 124 #define PHYSBOOTROM 0xffff0000 /* boot rom */ 125 126 #define VIRTIO PHYSIO 127