1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2023 Intel Corporation 3 */ 4 5 #ifndef _IDPF_LAN_PF_REGS_H_ 6 #define _IDPF_LAN_PF_REGS_H_ 7 8 9 /* Receive queues */ 10 #define PF_QRX_BASE 0x00000000 11 #define PF_QRX_TAIL(_QRX) (PF_QRX_BASE + (((_QRX) * 0x1000))) 12 #define PF_QRX_BUFFQ_BASE 0x03000000 13 #define PF_QRX_BUFFQ_TAIL(_QRX) (PF_QRX_BUFFQ_BASE + (((_QRX) * 0x1000))) 14 15 /* Transmit queues */ 16 #define PF_QTX_BASE 0x05000000 17 #define PF_QTX_COMM_DBELL(_DBQM) (PF_QTX_BASE + ((_DBQM) * 0x1000)) 18 19 20 /* Control(PF Mailbox) Queue */ 21 #define PF_FW_BASE 0x08400000 22 23 #define PF_FW_ARQBAL (PF_FW_BASE) 24 #define PF_FW_ARQBAH (PF_FW_BASE + 0x4) 25 #define PF_FW_ARQLEN (PF_FW_BASE + 0x8) 26 #define PF_FW_ARQLEN_ARQLEN_S 0 27 #define PF_FW_ARQLEN_ARQLEN_M GENMASK(12, 0) 28 #define PF_FW_ARQLEN_ARQVFE_S 28 29 #define PF_FW_ARQLEN_ARQVFE_M BIT(PF_FW_ARQLEN_ARQVFE_S) 30 #define PF_FW_ARQLEN_ARQOVFL_S 29 31 #define PF_FW_ARQLEN_ARQOVFL_M BIT(PF_FW_ARQLEN_ARQOVFL_S) 32 #define PF_FW_ARQLEN_ARQCRIT_S 30 33 #define PF_FW_ARQLEN_ARQCRIT_M BIT(PF_FW_ARQLEN_ARQCRIT_S) 34 #define PF_FW_ARQLEN_ARQENABLE_S 31 35 #define PF_FW_ARQLEN_ARQENABLE_M BIT(PF_FW_ARQLEN_ARQENABLE_S) 36 #define PF_FW_ARQH (PF_FW_BASE + 0xC) 37 #define PF_FW_ARQH_ARQH_S 0 38 #define PF_FW_ARQH_ARQH_M GENMASK(12, 0) 39 #define PF_FW_ARQT (PF_FW_BASE + 0x10) 40 41 #define PF_FW_ATQBAL (PF_FW_BASE + 0x14) 42 #define PF_FW_ATQBAH (PF_FW_BASE + 0x18) 43 #define PF_FW_ATQLEN (PF_FW_BASE + 0x1C) 44 #define PF_FW_ATQLEN_ATQLEN_S 0 45 #define PF_FW_ATQLEN_ATQLEN_M GENMASK(9, 0) 46 #define PF_FW_ATQLEN_ATQVFE_S 28 47 #define PF_FW_ATQLEN_ATQVFE_M BIT(PF_FW_ATQLEN_ATQVFE_S) 48 #define PF_FW_ATQLEN_ATQOVFL_S 29 49 #define PF_FW_ATQLEN_ATQOVFL_M BIT(PF_FW_ATQLEN_ATQOVFL_S) 50 #define PF_FW_ATQLEN_ATQCRIT_S 30 51 #define PF_FW_ATQLEN_ATQCRIT_M BIT(PF_FW_ATQLEN_ATQCRIT_S) 52 #define PF_FW_ATQLEN_ATQENABLE_S 31 53 #define PF_FW_ATQLEN_ATQENABLE_M BIT(PF_FW_ATQLEN_ATQENABLE_S) 54 #define PF_FW_ATQH (PF_FW_BASE + 0x20) 55 #define PF_FW_ATQH_ATQH_S 0 56 #define PF_FW_ATQH_ATQH_M GENMASK(9, 0) 57 #define PF_FW_ATQT (PF_FW_BASE + 0x24) 58 59 /* Interrupts */ 60 #define PF_GLINT_BASE 0x08900000 61 #define PF_GLINT_DYN_CTL(_INT) (PF_GLINT_BASE + ((_INT) * 0x1000)) 62 #define PF_GLINT_DYN_CTL_INTENA_S 0 63 #define PF_GLINT_DYN_CTL_INTENA_M BIT(PF_GLINT_DYN_CTL_INTENA_S) 64 #define PF_GLINT_DYN_CTL_CLEARPBA_S 1 65 #define PF_GLINT_DYN_CTL_CLEARPBA_M BIT(PF_GLINT_DYN_CTL_CLEARPBA_S) 66 #define PF_GLINT_DYN_CTL_SWINT_TRIG_S 2 67 #define PF_GLINT_DYN_CTL_SWINT_TRIG_M BIT(PF_GLINT_DYN_CTL_SWINT_TRIG_S) 68 #define PF_GLINT_DYN_CTL_ITR_INDX_S 3 69 #define PF_GLINT_DYN_CTL_ITR_INDX_M GENMASK(4, 3) 70 #define PF_GLINT_DYN_CTL_INTERVAL_S 5 71 #define PF_GLINT_DYN_CTL_INTERVAL_M BIT(PF_GLINT_DYN_CTL_INTERVAL_S) 72 #define PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_S 24 73 #define PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_S) 74 #define PF_GLINT_DYN_CTL_SW_ITR_INDX_S 25 75 #define PF_GLINT_DYN_CTL_SW_ITR_INDX_M BIT(PF_GLINT_DYN_CTL_SW_ITR_INDX_S) 76 #define PF_GLINT_DYN_CTL_WB_ON_ITR_S 30 77 #define PF_GLINT_DYN_CTL_WB_ON_ITR_M BIT(PF_GLINT_DYN_CTL_WB_ON_ITR_S) 78 #define PF_GLINT_DYN_CTL_INTENA_MSK_S 31 79 #define PF_GLINT_DYN_CTL_INTENA_MSK_M BIT(PF_GLINT_DYN_CTL_INTENA_MSK_S) 80 /* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is 81 * spacing b/w itrn registers of the same vector. 82 */ 83 #define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ 84 ((_reg_start) + ((_ITR) * (_itrn_indx_spacing))) 85 /* For PF, itrn_indx_spacing is 4 and itrn_reg_spacing is 0x1000 */ 86 #define PF_GLINT_ITR(_ITR, _INT) \ 87 (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000)) 88 #define PF_GLINT_ITR_MAX_INDEX 2 89 #define PF_GLINT_ITR_INTERVAL_S 0 90 #define PF_GLINT_ITR_INTERVAL_M GENMASK(11, 0) 91 92 /* Timesync registers */ 93 #define PF_TIMESYNC_BASE 0x08404000 94 #define PF_GLTSYN_CMD_SYNC (PF_TIMESYNC_BASE) 95 #define PF_GLTSYN_CMD_SYNC_EXEC_CMD_S 0 96 #define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M GENMASK(1, 0) 97 #define PF_GLTSYN_CMD_SYNC_SHTIME_EN_S 2 98 #define PF_GLTSYN_CMD_SYNC_SHTIME_EN_M BIT(PF_GLTSYN_CMD_SYNC_SHTIME_EN_S) 99 #define PF_GLTSYN_SHTIME_0 (PF_TIMESYNC_BASE + 0x4) 100 #define PF_GLTSYN_SHTIME_L (PF_TIMESYNC_BASE + 0x8) 101 #define PF_GLTSYN_SHTIME_H (PF_TIMESYNC_BASE + 0xC) 102 #define PF_GLTSYN_ART_L (PF_TIMESYNC_BASE + 0x10) 103 #define PF_GLTSYN_ART_H (PF_TIMESYNC_BASE + 0x14) 104 105 /* Generic registers */ 106 #define PF_INT_DIR_OICR_ENA 0x08406000 107 #define PF_INT_DIR_OICR_ENA_S 0 108 #define PF_INT_DIR_OICR_ENA_M GENMASK(31, 0) 109 #define PF_INT_DIR_OICR 0x08406004 110 #define PF_INT_DIR_OICR_TSYN_EVNT 0 111 #define PF_INT_DIR_OICR_PHY_TS_0 BIT(1) 112 #define PF_INT_DIR_OICR_PHY_TS_1 BIT(2) 113 #define PF_INT_DIR_OICR_CAUSE 0x08406008 114 #define PF_INT_DIR_OICR_CAUSE_CAUSE_S 0 115 #define PF_INT_DIR_OICR_CAUSE_CAUSE_M GENMASK(31, 0) 116 #define PF_INT_PBA_CLEAR 0x0840600C 117 118 #define PF_FUNC_RID 0x08406010 119 #define PF_FUNC_RID_FUNCTION_NUMBER_S 0 120 #define PF_FUNC_RID_FUNCTION_NUMBER_M GENMASK(2, 0) 121 #define PF_FUNC_RID_DEVICE_NUMBER_S 3 122 #define PF_FUNC_RID_DEVICE_NUMBER_M GENMASK(7, 3) 123 #define PF_FUNC_RID_BUS_NUMBER_S 8 124 #define PF_FUNC_RID_BUS_NUMBER_M GENMASK(15, 8) 125 126 /* Reset registers */ 127 #define PFGEN_RTRIG 0x08407000 128 #define PFGEN_RTRIG_CORER_S 0 129 #define PFGEN_RTRIG_CORER_M BIT(0) 130 #define PFGEN_RTRIG_LINKR_S 1 131 #define PFGEN_RTRIG_LINKR_M BIT(1) 132 #define PFGEN_RTRIG_IMCR_S 2 133 #define PFGEN_RTRIG_IMCR_M BIT(2) 134 #define PFGEN_RSTAT 0x08407008 /* PFR Status */ 135 #define PFGEN_RSTAT_PFR_STATE_S 0 136 #define PFGEN_RSTAT_PFR_STATE_M GENMASK(1, 0) 137 #define PFGEN_CTRL 0x0840700C 138 #define PFGEN_CTRL_PFSWR BIT(0) 139 140 #endif 141