| /openbsd-src/gnu/llvm/llvm/tools/llvm-tapi-diff/ |
| H A D | DiffEngine.cpp | 24 StringRef setOrderIndicator(InterfaceInputOrder Order) { in setOrderIndicator()
120 InterfaceInputOrder Order) { in addDiffForTargSlice()
139 std::string Name, InterfaceInputOrder Order) { in getSingleAttrDiff()
152 std::string Name, InterfaceInputOrder Order) { in getSingleAttrDiff()
163 std::string Name, InterfaceInputOrder Order) { in getSingleAttrDiff()
188 const T &Val, InterfaceInputOrder Order) { in diffAttribute()
193 InterfaceInputOrder Order) { in getSingleIF()
234 DiffOutput &Result, InterfaceInputOrder Order) { in findAndAddDiff()
252 DiffOutput &Result, InterfaceInputOrder Order) { in findAndAddDiff()
265 DiffOutput &Result, InterfaceInputOrder Order) { in findAndAddDiff()
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| H A D | DiffEngine.h | 64 DiffScalarVal(InterfaceInputOrder Order, T Val) in DiffScalarVal()
83 SymScalar(InterfaceInputOrder Order, const MachO::Symbol *Sym) in SymScalar()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.h | 32 ArrayRef<MCPhysReg> Order; variable
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder()
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| H A D | RegAllocGreedy.cpp | 395 AllocationOrder &Order, in tryAssign()
449 auto Order = in canReassign() local
528 const AllocationOrder &Order, in getOrderLimit()
574 AllocationOrder &Order, in tryEvict()
847 const AllocationOrder &Order) { in calcGlobalSplitCost()
1039 AllocationOrder &Order, in tryRegionSplit()
1072 AllocationOrder &Order, in calculateRegionSplitCost()
1204 AllocationOrder &Order, in tryBlockSplit()
1317 AllocationOrder &Order, in tryInstructionSplit()
1470 AllocationOrder &Order, in tryLocalSplit()
[all …]
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| H A D | AllocationOrder.cpp | 34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create() local
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| H A D | LocalStackSlotAllocation.cpp | 58 unsigned Order; member in __anon0b13e6740111::FrameRef
304 unsigned Order = 0; in insertFrameReferenceRegisters() local
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| H A D | BreakFalseDeps.cpp | 156 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef() local
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| H A D | RegAllocBasic.cpp | 265 auto Order = in selectOrSplit() local
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| H A D | RegAllocEvictionAdvisor.cpp | 276 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate()
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| H A D | TargetRegisterInfo.cpp | 251 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); in getAllocatableSetForRC() local
423 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
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| H A D | CriticalAntiDepBreaker.cpp | 406 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister() local
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| /openbsd-src/gnu/llvm/llvm/include/llvm/Frontend/OpenMP/ |
| H A D | OMPIRBuilder.h | 1954 explicit OffloadEntryInfo(OffloadingEntryInfoKinds Kind, unsigned Order, in OffloadEntryInfo()
1980 unsigned Order = ~0u; variable
2014 explicit OffloadEntryInfoTargetRegion(unsigned Order, Constant *Addr, in OffloadEntryInfoTargetRegion()
2077 explicit OffloadEntryInfoDeviceGlobalVar(unsigned Order, in OffloadEntryInfoDeviceGlobalVar()
2080 explicit OffloadEntryInfoDeviceGlobalVar(unsigned Order, Constant *Addr, in OffloadEntryInfoDeviceGlobalVar()
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| /openbsd-src/gnu/llvm/llvm/lib/Support/ |
| H A D | DynamicLibrary.cpp | 81 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in LibLookup()
96 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in Lookup()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SDNodeDbgValue.h | 149 unsigned Order; variable
245 unsigned Order; variable
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| H A D | ScheduleDAGSDNodes.cpp | 738 DenseMap<SDValue, Register> &VRBaseMap, unsigned Order) { in ProcessSDDbgValues()
786 unsigned Order = N->getIROrder(); in ProcessSourceNode() local
981 unsigned Order = Orders[i].first; in EmitSchedule() local
1027 unsigned Order = InstrOrder.first; in EmitSchedule() local
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| /openbsd-src/games/mille/ |
| H A D | extern.c | 43 Order, /* set if hand should be sorted */ variable
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| /openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 36 std::unique_ptr<MCPhysReg[]> Order; member
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| /openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 57 static void addHints(ArrayRef<MCPhysReg> Order, in addHints()
75 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
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| /openbsd-src/gnu/llvm/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 545 unsigned Order = 0; // Cache the sort key. member
787 unsigned getRegSetIDAt(unsigned Order) const { in getRegSetIDAt()
791 const RegUnitSet &getRegSetAt(unsigned Order) const { in getRegSetAt()
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| H A D | RegisterInfoEmitter.cpp | 1048 ArrayRef<Record*> Order = RC.getOrder(); in runMCDesc() local
1084 ArrayRef<Record *> Order = RC.getOrder(); in runMCDesc() local
1249 ArrayRef<Record*> Order = RC.getOrder(); in runTargetDesc() local
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| /openbsd-src/gnu/llvm/llvm/tools/llvm-profgen/ |
| H A D | CSPreInliner.cpp | 76 std::vector<StringRef> Order; in buildTopDownOrder() local
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| /openbsd-src/gnu/llvm/llvm/lib/Transforms/Utils/ |
| H A D | CodeLayout.cpp | 885 void concatChains(std::vector<uint64_t> &Order) { in concatChains()
978 const std::vector<uint64_t> &Order, const std::vector<uint64_t> &NodeSizes, in calcExtTspScore()
1009 std::vector<uint64_t> Order(NodeSizes.size()); in calcExtTspScore() local
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| /openbsd-src/gnu/llvm/libcxx/benchmarks/algorithms/ |
| H A D | common.h | 32 enum class Order { enum
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInsertDelayAlu.cpp | 241 SmallVector<const_iterator, 8> Order; in dump() local
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| /openbsd-src/gnu/llvm/clang/lib/CodeGen/ |
| H A D | CGAtomic.cpp | 524 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp()
726 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp()
850 llvm::Value *Order = EmitScalarExpr(E->getOrder()); in EmitAtomicExpr() local
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