| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.h | 32 ArrayRef<MCPhysReg> Order; variable
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder()
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| H A D | RegAllocGreedy.cpp | 800 AllocationOrder &Order, in tryAssign()
854 auto Order = in canReassign() local
1067 MCRegister RAGreedy::getCheapestEvicteeWeight(const AllocationOrder &Order, in getCheapestEvicteeWeight()
1150 MCRegister RAGreedy::tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, in tryEvict()
1525 const AllocationOrder &Order) { in splitCanCauseEvictionChain()
1584 const AllocationOrder &Order) { in splitCanCauseLocalSpill()
1605 const AllocationOrder &Order, in calcGlobalSplitCost()
1837 AllocationOrder &Order, in tryRegionSplit()
1881 AllocationOrder &Order, in calculateRegionSplitCost()
2027 unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryBlockSplit()
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| H A D | AllocationOrder.cpp | 34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create() local
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| H A D | LocalStackSlotAllocation.cpp | 59 unsigned Order; member in __anon63de47a80111::FrameRef
302 unsigned Order = 0; in insertFrameReferenceRegisters() local
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| H A D | BreakFalseDeps.cpp | 153 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef() local
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| H A D | RegAllocBasic.cpp | 267 auto Order = in selectOrSplit() local
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| H A D | TargetRegisterInfo.cpp | 250 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); in getAllocatableSetForRC() local
422 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
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| H A D | CriticalAntiDepBreaker.cpp | 402 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Support/ |
| H A D | DynamicLibrary.cpp | 74 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in LibLookup()
89 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in Lookup()
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| /netbsd-src/external/gpl3/gcc.old/dist/libphobos/src/std/digest/ |
| H A D | digest.d | 15 alias Order = _newDigest.Order; variable
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| /netbsd-src/usr.sbin/ypserv/yptest/ |
| H A D | yptest.c | 54 int KeyLen, ValLen, Status, Order; in main() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SDNodeDbgValue.h | 148 unsigned Order; variable
244 unsigned Order; variable
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| H A D | ScheduleDAGSDNodes.cpp | 738 DenseMap<SDValue, Register> &VRBaseMap, unsigned Order) { in ProcessSDDbgValues()
786 unsigned Order = N->getIROrder(); in ProcessSourceNode() local
979 unsigned Order = Orders[i].first; in EmitSchedule() local
1025 unsigned Order = InstrOrder.first; in EmitSchedule() local
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| H A D | SelectionDAGDumper.cpp | 818 if (unsigned Order = getIROrder()) in print_details() local
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| /netbsd-src/games/mille/ |
| H A D | extern.c | 51 Order, /* set if hand should be sorted */ variable
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 37 std::unique_ptr<MCPhysReg[]> Order; member
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| H A D | ScheduleDAG.h | 56 Order ///< Any other ordering dependency. enumerator
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| /netbsd-src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| H A D | CGOpenMPRuntime.h | 523 explicit OffloadEntryInfo(OffloadingEntryInfoKinds Kind, unsigned Order, in OffloadEntryInfo()
551 unsigned Order = ~0u; variable
584 explicit OffloadEntryInfoTargetRegion(unsigned Order, in OffloadEntryInfoTargetRegion()
645 explicit OffloadEntryInfoDeviceGlobalVar(unsigned Order, in OffloadEntryInfoDeviceGlobalVar()
649 unsigned Order, llvm::Constant *Addr, CharUnits VarSize, in OffloadEntryInfoDeviceGlobalVar()
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| H A D | CGAtomic.cpp | 515 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp()
705 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp()
829 llvm::Value *Order = EmitScalarExpr(E->getOrder()); in EmitAtomicExpr() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-profgen/ |
| H A D | CSPreInliner.cpp | 44 std::vector<StringRef> Order; in buildTopDownOrder() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 57 static void addHints(ArrayRef<MCPhysReg> Order, in addHints()
75 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 519 unsigned Order = 0; // Cache the sort key. member
746 unsigned getRegSetIDAt(unsigned Order) const { in getRegSetIDAt()
750 const RegUnitSet &getRegSetAt(unsigned Order) const { in getRegSetAt()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/IR/ |
| H A D | BasicBlock.cpp | 500 unsigned Order = 0; in renumberInstructions() local
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| /netbsd-src/external/apache2/llvm/dist/libcxx/benchmarks/ |
| H A D | algorithms.bench.cpp | 35 enum class Order { enum
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| /netbsd-src/external/apache2/llvm/dist/llvm/tools/verify-uselistorder/ |
| H A D | verify-uselistorder.cpp | 407 SmallDenseMap<const Use *, short, 16> Order; in shuffleValueUseLists() local
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