| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.h | 32 ArrayRef<MCPhysReg> Order; variable
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder()
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| H A D | RegAllocGreedy.cpp | 534 unsigned OrderLimit = Order.getOrder().size(); in getOrderLimit() argument
400 tryAssign(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs,const SmallVirtRegSet & FixedRegisters) tryAssign() argument
580 tryEvict(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs,uint8_t CostPerUseLimit,const SmallVirtRegSet & FixedRegisters) tryEvict() argument
871 calcGlobalSplitCost(GlobalSplitCandidate & Cand,const AllocationOrder & Order) calcGlobalSplitCost() argument
1063 tryRegionSplit(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs) tryRegionSplit() argument
1097 calculateRegionSplitCostAroundReg(MCPhysReg PhysReg,AllocationOrder & Order,BlockFrequency & BestCost,unsigned & NumCands,unsigned & BestCand) calculateRegionSplitCostAroundReg() argument
1174 calculateRegionSplitCost(const LiveInterval & VirtReg,AllocationOrder & Order,BlockFrequency & BestCost,unsigned & NumCands,bool IgnoreCSR) calculateRegionSplitCost() argument
1236 trySplitAroundHintReg(MCPhysReg Hint,const LiveInterval & VirtReg,SmallVectorImpl<Register> & NewVRegs,AllocationOrder & Order) trySplitAroundHintReg() argument
1296 tryBlockSplit(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs) tryBlockSplit() argument
1417 tryInstructionSplit(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs) tryInstructionSplit() argument
1570 tryLocalSplit(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs) tryLocalSplit() argument
1800 trySplit(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs,const SmallVirtRegSet & FixedRegisters) trySplit() argument
1957 tryLastChanceRecoloring(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs,SmallVirtRegSet & FixedRegisters,RecoloringStack & RecolorStack,unsigned Depth) tryLastChanceRecoloring() argument
2177 tryAssignCSRFirstTime(const LiveInterval & VirtReg,AllocationOrder & Order,MCRegister PhysReg,uint8_t & CostPerUseLimit,SmallVectorImpl<Register> & NewVRegs) tryAssignCSRFirstTime() argument
2417 auto Order = selectOrSplitImpl() local
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| H A D | AllocationOrder.cpp | 34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create() local
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| H A D | LocalStackSlotAllocation.cpp | 58 unsigned Order; global() member in __anon34883f2f0111::FrameRef
304 unsigned Order = 0; insertFrameReferenceRegisters() local
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| H A D | RegAllocBasic.cpp | 265 auto Order = selectOrSplit() local
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| H A D | BreakFalseDeps.cpp | 156 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef() local
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| H A D | RegAllocEvictionAdvisor.cpp | 276 tryFindEvictionCandidate(const LiveInterval & VirtReg,const AllocationOrder & Order,uint8_t CostPerUseLimit,const SmallVirtRegSet & FixedRegisters) const tryFindEvictionCandidate() argument
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| H A D | TargetRegisterInfo.cpp | 252 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); getAllocatableSetForRC() local
424 getRegAllocationHints(Register VirtReg,ArrayRef<MCPhysReg> Order,SmallVectorImpl<MCPhysReg> & Hints,const MachineFunction & MF,const VirtRegMap * VRM,const LiveRegMatrix * Matrix) const getRegAllocationHints() argument
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| H A D | CriticalAntiDepBreaker.cpp | 399 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister() local
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| H A D | MLRegAllocEvictAdvisor.cpp | 664 tryFindEvictionCandidate(const LiveInterval & VirtReg,const AllocationOrder & Order,uint8_t CostPerUseLimit,const SmallVirtRegSet & FixedRegisters) const tryFindEvictionCandidate() argument
1085 tryFindEvictionCandidatePosition(const LiveInterval & VirtReg,const AllocationOrder & Order,unsigned OrderLimit,uint8_t CostPerUseLimit,const SmallVirtRegSet & FixedRegisters) const tryFindEvictionCandidatePosition() argument
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SDNodeDbgValue.h | 149 unsigned Order; variable
245 unsigned Order; variable
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| H A D | ScheduleDAGSDNodes.cpp | 739 ProcessSDDbgValues(SDNode * N,SelectionDAG * DAG,InstrEmitter & Emitter,SmallVectorImpl<std::pair<unsigned,MachineInstr * >> & Orders,DenseMap<SDValue,Register> & VRBaseMap,unsigned Order) ProcessSDDbgValues() argument
787 unsigned Order = N->getIROrder(); ProcessSourceNode() local
982 unsigned Order = Orders[i].first; EmitSchedule() local
1028 unsigned Order = InstrOrder.first; EmitSchedule() local
[all...] |
| H A D | SelectionDAGDumper.cpp | 861 if (unsigned Order = getIROrder()) print_details() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Support/ |
| H A D | DynamicLibrary.cpp | 81 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in LibLookup()
96 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in Lookup()
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 36 std::unique_ptr<MCPhysReg[]> Order; member
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| H A D | ScheduleDAG.h | 56 Order ///< Any other ordering dependency. enumerator
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 57 static void addHints(ArrayRef<MCPhysReg> Order, in addHints()
75 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/Frontend/OpenMP/ |
| H A D | OMPIRBuilder.h | 248 : Flags(Flags), Order(Order), Kind(Kind) {} variable
222 OffloadEntryInfo(OffloadingEntryInfoKinds Kind,unsigned Order,uint32_t Flags) OffloadEntryInfo() argument
278 OffloadEntryInfoTargetRegion(unsigned Order,Constant * Addr,Constant * ID,OMPTargetRegionEntryKind Flags) OffloadEntryInfoTargetRegion() argument
364 OffloadEntryInfoDeviceGlobalVar(unsigned Order,OMPTargetGlobalVarEntryKind Flags) OffloadEntryInfoDeviceGlobalVar() argument
367 OffloadEntryInfoDeviceGlobalVar(unsigned Order,Constant * Addr,int64_t VarSize,OMPTargetGlobalVarEntryKind Flags,GlobalValue::LinkageTypes Linkage,const std::string & VarName) OffloadEntryInfoDeviceGlobalVar() argument
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| /freebsd-src/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | |
| H A D | RegisterInfoEmitter.cpp | 1024 ArrayRef<Record*> Order = RC.getOrder(); runMCDesc() local
1060 ArrayRef<Record *> Order = RC.getOrder(); runMCDesc() local
1225 ArrayRef<Record*> Order = RC.getOrder(); runTargetDesc() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | CodeLayout.cpp | 1001 std::vector<uint64_t> Order; in concatChains() local
1368 std::vector<uint64_t> Order; in concatChains() local
1428 double codelayout::calcExtTspScore(ArrayRef<uint64_t> Order, in calcExtTspScore()
1454 std::vector<uint64_t> Order(NodeSizes.size()); in calcExtTspScore() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInsertDelayAlu.cpp | 247 SmallVector<const_iterator, 8> Order; in dump() local
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| /freebsd-src/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGAtomic.cpp | 525 EmitAtomicOp(CodeGenFunction & CGF,AtomicExpr * E,Address Dest,Address Ptr,Address Val1,Address Val2,llvm::Value * IsWeak,llvm::Value * FailureOrder,uint64_t Size,llvm::AtomicOrdering Order,llvm::SyncScope::ID Scope) EmitAtomicOp() argument
759 EmitAtomicOp(CodeGenFunction & CGF,AtomicExpr * Expr,Address Dest,Address Ptr,Address Val1,Address Val2,llvm::Value * IsWeak,llvm::Value * FailureOrder,uint64_t Size,llvm::AtomicOrdering Order,llvm::Value * Scope) EmitAtomicOp() argument
881 llvm::Value *Order = EmitScalarExpr(E->getOrder()); EmitAtomicExpr() local
[all...] |
| /freebsd-src/contrib/llvm-project/clang/lib/Format/ |
| H A D | QualifierAlignmentFixer.cpp | 578 prepareLeftRightOrderingForQualifierAlignmentFixer(const std::vector<std::string> & Order,std::vector<std::string> & LeftOrder,std::vector<std::string> & RightOrder,std::vector<tok::TokenKind> & Qualifiers) prepareLeftRightOrderingForQualifierAlignmentFixer() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.cpp | 752 getRegAllocationHints(Register VirtReg,ArrayRef<MCPhysReg> Order,SmallVectorImpl<MCPhysReg> & Hints,const MachineFunction & MF,const VirtRegMap * VRM,const LiveRegMatrix * Matrix) const getRegAllocationHints() argument
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