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Searched defs:OpRC (Results 1 – 8 of 8) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DBreakFalseDeps.cpp134 const TargetRegisterClass *OpRC = in pickBestRegisterForUndef() local
H A DRegAllocFast.cpp1064 const TargetRegisterClass *OpRC = MRI->getRegClass(Reg); in addRegClassDefCounts() local
H A DMachineInstr.cpp951 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp320 const TargetRegisterClass *OpRC = nullptr; in AddRegisterOperand() local
389 const TargetRegisterClass *OpRC = in AddOperand() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp812 const TargetRegisterClass *OpRC = in processPHINode() local
H A DSIInstrInfo.cpp5091 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand() local
5400 const TargetRegisterClass *OpRC = in legalizeOperands() local
5462 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); in legalizeOperands() local
6922 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass); in findUsedSGPR() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86SpeculativeLoadHardening.cpp1662 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonBitSimplify.cpp1886 auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF); in validateReg() local