| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/Disassembler/ |
| H A D | XCoreDisassembler.cpp | 259 unsigned &Op3) { in Decode3OpInstruction()
538 unsigned Op1, Op2, Op3; in Decode3RInstruction() local
551 unsigned Op1, Op2, Op3; in Decode3RImmInstruction() local
564 unsigned Op1, Op2, Op3; in Decode2RUSInstruction() local
577 unsigned Op1, Op2, Op3; in Decode2RUSBitpInstruction() local
590 unsigned Op1, Op2, Op3; in DecodeL3RInstruction() local
604 unsigned Op1, Op2, Op3; in DecodeL3RSrcDstInstruction() local
619 unsigned Op1, Op2, Op3; in DecodeL2RUSInstruction() local
633 unsigned Op1, Op2, Op3; in DecodeL2RUSBitpInstruction() local
647 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGTargetInfo.h | 53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy()
69 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, in EmitTargetCodeForMemmove()
82 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset()
94 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblySelectionDAGInfo.cpp | 38 SDValue Op3, Align Alignment, bool IsVolatile, in EmitTargetCodeForMemmove()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrBuilder.h | 110 const MachineOperand &Op3 = MI->getOperand(Operand + 3); in getAddressFromInstr() local
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| H A D | X86FastISel.cpp | 3956 unsigned Op2, unsigned Op3) { in fastEmitInst_rrrr()
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| H A D | X86InstrInfo.cpp | 1826 unsigned Op1 = 1, Op2 = 2, Op3 = 3; in getThreeSrcCommuteCase() local
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| H A D | X86ISelDAGToDAG.cpp | 5974 SDValue Op0, Op1, Op2, Op3, Op4; in SelectInlineAsmMemoryOperand() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/AsmParser/ |
| H A D | BPFAsmParser.cpp | 271 BPFOperand &Op3 = (BPFOperand &)*Operands[3]; in PreMatchCheck() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1257 const MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1281 const MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1314 MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
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| H A D | HexagonSplitDouble.cpp | 905 MachineOperand &Op3 = MI->getOperand(3); in splitAslOr() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 4755 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
4841 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
4905 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
4964 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 8207 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) { in UpdateNodeOperands()
8214 SDValue Op3, SDValue Op4) { in UpdateNodeOperands()
8221 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands()
8315 SDValue Op2, SDValue Op3) { in SelectNodeTo()
8522 SDValue Op3) { in getMachineNode()
8544 SDValue Op2, SDValue Op3) { in getMachineNode()
8568 SDValue Op3) { in getMachineNode()
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| H A D | SelectionDAGBuilder.cpp | 5828 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
5870 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
5885 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
6459 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
6470 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
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| H A D | LegalizeIntegerTypes.cpp | 309 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); in PromoteIntRes_AtomicCmpSwap() local
1981 SDValue Op3 = ZExtPromotedInteger(N->getOperand(3)); in PromoteIntOp_PREFETCH() local
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| H A D | LegalizeFloatTypes.cpp | 2787 SDValue Op3 = GetSoftPromotedHalf(N->getOperand(3)); in SoftPromoteHalfRes_SELECT_CC() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 78 const MCOperand &Op3 = MI->getOperand(3); in printInst() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 227 unsigned Reg2, MCOperand Op3, SMLoc IDLoc, in emitRRRX()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 237 unsigned Op3) { in fastEmitInst_riir()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| H A D | ConstantFolding.cpp | 2725 if (const auto *Op3 = dyn_cast<ConstantFP>(Operands[2])) { in ConstantFoldScalarCall3() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 6622 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]); in tryConvertingToTwoOperandForm() local
6945 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); in fixupGNULDRDAlias() local
7027 const MCParsedAsmOperand &Op3 = *Operands[3 + NumPredOps]; in CDEConvertDualRegOperand() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| H A D | PatternMatch.h | 1454 T2 Op3; member
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/IR/ |
| H A D | Verifier.cpp | 5148 auto *Op3 = cast<ConstantInt>(Call.getArgOperand(2)); in visitIntrinsicCall() local
|