/netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
H A D | InstructionSimplify.cpp | 299 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS); in SimplifyAssociativeBinOp() local 597 Value *&Op0, Value *&Op1, in foldOrCommuteConstant() 612 static Value *SimplifyAddInst(Value *Op0, Value *Op1, bool IsNSW, bool IsNUW, in SimplifyAddInst() 676 Value *llvm::SimplifyAddInst(Value *Op0, Value *Op1, bool IsNSW, bool IsNUW, in SimplifyAddInst() 731 static Value *SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, in SimplifySubInst() 859 Value *llvm::SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, in SimplifySubInst() 866 static Value *SimplifyMulInst(Value *Op0, Value *Op1, const SimplifyQuery &Q, in SimplifyMulInst() 920 Value *llvm::SimplifyMulInst(Value *Op0, Value *Op1, const SimplifyQuery &Q) { in SimplifyMulInst() 926 static Value *simplifyDivRem(Value *Op0, Value *Op1, bool IsDiv, in simplifyDivRem() 1045 static Value *simplifyDiv(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, in simplifyDiv() [all …]
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H A D | OverflowInstAnalysis.cpp | 22 bool llvm::isCheckForZeroAndMulWithOverflow(Value *Op0, Value *Op1, bool IsAnd, in isCheckForZeroAndMulWithOverflow() 68 bool llvm::isCheckForZeroAndMulWithOverflow(Value *Op0, Value *Op1, in isCheckForZeroAndMulWithOverflow()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineMulDivRem.cpp | 156 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitMul() local 400 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in foldFPSignBitOps() local 450 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitFMul() local 724 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in commonIDivTransforms() local 887 static Instruction *foldUDivPow2Cst(Value *Op0, Value *Op1, in foldUDivPow2Cst() 901 static Instruction *foldUDivShl(Value *Op0, Value *Op1, const BinaryOperator &I, in foldUDivShl() 927 static size_t visitUDivOperand(Value *Op0, Value *Op1, const BinaryOperator &I, in visitUDivOperand() 1013 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitUDiv() local 1107 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitSDiv() local 1280 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in foldFDivPowDivisor() local [all …]
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H A D | InstCombineAndOrXor.cpp | 1225 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); in foldAndOfICmps() local 1493 Value *Op0 = BO.getOperand(0), *Op1 = BO.getOperand(1), *X; in reassociateFCmps() local 1611 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in foldCastedBitwiseLogic() local 1676 Value *Op0 = I.getOperand(0); in foldAndToXor() local 1702 Value *Op0 = I.getOperand(0); in foldOrToXor() local 1748 Value *Op0 = And.getOperand(0), *Op1 = And.getOperand(1); in narrowMaskedBinOp() local 1813 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitAnd() local 2217 Value *Op0 = Or.getOperand(0), *Op1 = Or.getOperand(1); in matchOrConcat() local 2657 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitOr() local 2985 Value *Op0 = I.getOperand(0); in foldXorToXor() local [all …]
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H A D | InstCombineShifts.cpp | 373 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in commonShiftTransforms() local 662 Instruction *InstCombinerImpl::FoldShiftByConstant(Value *Op0, Constant *Op1, in FoldShiftByConstant() 907 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitShl() local 1049 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitLShr() local 1271 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitAShr() local
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H A D | InstCombineAddSub.cpp | 826 Value *Op0 = Add.getOperand(0), *Op1 = Add.getOperand(1); in foldNoWrapAdd() local 865 Value *Op0 = Add.getOperand(0), *Op1 = Add.getOperand(1); in foldAddWithConstant() local 1259 auto *Op0 = dyn_cast<BinaryOperator>(I.getOperand(0)); in factorizeMathWithShlOps() local 1489 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in factorizeFAddFSub() local 1719 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitSub() local 2241 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitFSub() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZTDC.cpp | 131 Value *Op0 = I.getOperand(0); in convertFCmp() local 241 Value *Op0 = I.getOperand(0); in convertICmp() local 296 Value *Op0, *Op1; in convertLogicOp() local
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H A D | SystemZISelDAGToDAG.cpp | 444 SDValue Op0, uint64_t Op1) { in expandDisp() 467 SDValue Op0 = N.getOperand(0); in expandAddress() local 1085 SDValue Op0 = N->getOperand(I ^ 1); in tryRxSBG() local 1116 SDValue Op0, uint64_t UpperVal, in splitLargeImmediate() 1548 auto Op0 = Node->getOperand(0); in Select() local 1589 SDValue Op0 = Node->getOperand(0); in Select() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
H A D | Scalarizer.cpp | 498 Value *Op0 = VOp0[Elem]; in splitBinary() local 595 Value *Op0 = VOp0[I]; in visitSelectInst() local 602 Value *Op0 = SI.getOperand(0); in visitSelectInst() local 641 Value *Op0 = GEPI.getOperand(0); in visitGetElementPtrInst() local 683 Scatterer Op0 = scatter(&CI, CI.getOperand(0)); in visitCastInst() local 703 Scatterer Op0 = scatter(&BCI, BCI.getOperand(0)); in visitBitCastInst() local 756 Scatterer Op0 = scatter(&IEI, IEI.getOperand(0)); in visitInsertElementInst() local 791 Scatterer Op0 = scatter(&EEI, EEI.getOperand(0)); in visitExtractElementInst() local 822 Scatterer Op0 = scatter(&SVI, SVI.getOperand(0)); in visitShuffleVectorInst() local
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H A D | ConstraintElimination.cpp | 57 Value *Op0, *Op1; in decompose() local 96 Value *Op0; in decompose() local 128 getConstraint(CmpInst::Predicate Pred, Value *Op0, Value *Op1, in getConstraint() 287 Value *Op0, *Op1; in eliminateConstraints() local
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | MachineIRBuilder.h | 487 MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, in buildPtrMask() 521 const SrcOp &Op0, const SrcOp &Op1) { in buildUAddo() 527 const SrcOp &Op0, const SrcOp &Op1) { in buildUSubo() 533 const SrcOp &Op0, const SrcOp &Op1) { in buildSAddo() 539 const SrcOp &Op0, const SrcOp &Op1) { in buildSSubo() 558 const SrcOp &Op0, const SrcOp &Op1, in buildUAdde() 566 const SrcOp &Op0, const SrcOp &Op1, in buildUSube() 574 const SrcOp &Op0, const SrcOp &Op1, in buildSAdde() 582 const SrcOp &Op0, const SrcOp &Op1, in buildSSube()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 491 Register Op0 = getRegForValue(I->getOperand(0)); in selectBinaryOp() local 1408 Register Op0 = getRegForValue(I->getOperand(0)); in selectBitCast() local 1655 const Value *Op0 = EVI->getOperand(0); in selectExtractValue() local 1860 Register FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, in fastEmit_ri_() 1926 const TargetRegisterClass *RC, unsigned Op0) { in fastEmitInst_r() 1946 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rr() 1969 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rrr() 1995 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_ri() 2017 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rii() 2060 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rri() [all …]
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H A D | LegalizeFloatTypes.cpp | 857 SDValue Op0 = GetSoftenedFloat(N->getOperand(0)); in SoftenFloatOp_BITCAST() local 1002 SDValue Op0 = N->getOperand(IsStrict ? 1 : 0); in SoftenFloatOp_SETCC() local 2165 SDValue Op0 = GetPromotedFloat(N->getOperand(0)); in PromoteFloatOp_SETCC() local 2390 SDValue Op0 = GetPromotedFloat(N->getOperand(0)); in PromoteFloatRes_FCOPYSIGN() local 2414 SDValue Op0 = GetPromotedFloat(N->getOperand(0)); in PromoteFloatRes_BinOp() local 2422 SDValue Op0 = GetPromotedFloat(N->getOperand(0)); in PromoteFloatRes_FMAD() local 2433 SDValue Op0 = GetPromotedFloat(N->getOperand(0)); in PromoteFloatRes_FPOWI() local 2720 SDValue Op0 = GetSoftPromotedHalf(N->getOperand(0)); in SoftPromoteHalfRes_FMAD() local 2738 SDValue Op0 = GetSoftPromotedHalf(N->getOperand(0)); in SoftPromoteHalfRes_FPOWI() local 2823 SDValue Op0 = GetSoftPromotedHalf(N->getOperand(0)); in SoftPromoteHalfRes_BinOp() local [all …]
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H A D | TargetLowering.cpp | 761 SDValue Op0 = Op.getOperand(0); in SimplifyMultipleUseDemandedBits() local 772 SDValue Op0 = Op.getOperand(0); in SimplifyMultipleUseDemandedBits() local 794 SDValue Op0 = Op.getOperand(0); in SimplifyMultipleUseDemandedBits() local 1152 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local 1185 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local 1262 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local 1305 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local 1414 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local 1442 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local 1550 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local [all …]
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H A D | SelectionDAGAddressAnalysis.cpp | 86 bool BaseIndexOffset::computeAliasing(const SDNode *Op0, in computeAliasing()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/IR/ |
H A D | AutoUpgrade.cpp | 1127 Value *Op0, Value *Op1) { in EmitX86Select() 1139 Value *Op0, Value *Op1) { in EmitX86ScalarSelect() 1155 static Value *UpgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0, in UpgradeX86ALIGNIntrinsics() 1265 Value *Op0 = CI.getOperand(0); in UpgradeX86BinaryIntrinsics() local 1347 Value *Op0 = CI.getArgOperand(0); in upgradeX86ConcatShift() local 1426 Value *Op0 = CI.getArgOperand(0); in upgradeAbs() local 1488 Value *Op0 = CI.getArgOperand(0); in upgradeMaskedCompare() local 1981 Value *Op0 = CI->getArgOperand(0); in UpgradeIntrinsicCall() local 2580 Value *Op0 = CI->getArgOperand(0); in UpgradeIntrinsicCall() local 2594 Value *Op0 = CI->getArgOperand(0); in UpgradeIntrinsicCall() local [all …]
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.cpp | 142 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local 156 uint32_t Op0 = (Bits >> 14) & 0x3; in genericRegisterString() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86RegisterBankInfo.cpp | 213 auto &Op0 = MI.getOperand(0); in getInstrMapping() local 242 auto &Op0 = MI.getOperand(0); in getInstrMapping() local
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H A D | X86InstCombineIntrinsic.cpp | 620 static Value *simplifyX86extrq(IntrinsicInst &II, Value *Op0, in simplifyX86extrq() 711 static Value *simplifyX86insertq(IntrinsicInst &II, Value *Op0, Value *Op1, in simplifyX86insertq() 1466 Value *Op0 = II.getArgOperand(0); in instCombineIntrinsic() local 1508 Value *Op0 = II.getArgOperand(0); in instCombineIntrinsic() local 1531 Value *Op0 = II.getArgOperand(0); in instCombineIntrinsic() local 1567 Value *Op0 = II.getArgOperand(0); in instCombineIntrinsic() local 1612 Value *Op0 = II.getArgOperand(0); in instCombineIntrinsic() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
H A D | MachineIRBuilder.cpp | 165 void MachineIRBuilder::validateUnaryOp(const LLT Res, const LLT Op0) { in validateUnaryOp() 170 void MachineIRBuilder::validateBinaryOp(const LLT Res, const LLT Op0, in validateBinaryOp() 176 void MachineIRBuilder::validateShiftOp(const LLT Res, const LLT Op0, in validateShiftOp() 183 const SrcOp &Op0, in buildPtrAdd() 193 MachineIRBuilder::materializePtrAdd(Register &Res, Register Op0, in materializePtrAdd() 209 const SrcOp &Op0, in buildMaskLowPtrBits() 750 const SrcOp &Op0, in buildICmp() 757 const SrcOp &Op0, in buildFCmp() 766 const SrcOp &Op0, in buildSelect()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUInstCombineIntrinsic.cpp | 170 bool GCNTTIImpl::canSimplifyLegacyMulToMul(const Value *Op0, const Value *Op1, in canSimplifyLegacyMulToMul() 806 Value *Op0 = II.getArgOperand(0); in instCombineIntrinsic() local 852 Value *Op0 = II.getArgOperand(0); in instCombineIntrinsic() local 872 Value *Op0 = II.getArgOperand(0); in instCombineIntrinsic() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/AggressiveInstCombine/ |
H A D | AggressiveInstCombine.cpp | 220 Value *Op0, *Op1; in matchAndOrChain() local 328 Value *Op0 = I.getOperand(0); in tryToRecognizePopCount() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonSplitDouble.cpp | 699 MachineOperand &Op0 = MI->getOperand(0); in splitImmediate() local 726 MachineOperand &Op0 = MI->getOperand(0); in splitCombine() local 756 MachineOperand &Op0 = MI->getOperand(0); in splitExt() local 778 MachineOperand &Op0 = MI->getOperand(0); in splitShift() local 902 MachineOperand &Op0 = MI->getOperand(0); in splitAslOr() local
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
H A D | GetElementPtrTypeIterator.h | 163 gep_type_begin(Type *Op0, ArrayRef<T> A) { in gep_type_begin()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
H A D | PredicateInfo.cpp | 380 auto *Op0 = Comparison->getOperand(0); in collectCmpOps() local 414 Value *Op0, *Op1; in processAssume() local 459 Value *Op0, *Op1; in processBranch() local
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