Searched defs:Offset0 (Results 1 – 9 of 9) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMHazardRecognizer.cpp | 190 int64_t Offset0 = 0; in getHazardType() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 347 int64_t Offset0; in apply() local
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| H A D | HexagonISelLoweringHVX.cpp | 1729 SDValue Offset0 = DAG.getTargetConstant(0, dl, ty(Base)); in LowerHvxMaskedOp() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 1278 bool AMDGPUDAGToDAGISel::isDSOffset2Legal(SDValue Base, unsigned Offset0, in isDSOffset2Legal()
1297 SDValue &Offset0, in SelectDS64Bit4ByteAligned()
1303 SDValue &Offset0, in SelectDS128Bit8ByteAligned()
1309 SDValue &Offset0, SDValue &Offset1, in SelectDSReadWrite2()
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| H A D | SIInstrInfo.cpp | 130 int64_t &Offset0, in areLoadsFromSameBasePtr()
282 unsigned Offset0 = Offset0Op->getImm(); in getMemOperandsWithOffsetWidth() local
471 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear()
2948 int64_t Offset0, Offset1; in checkInstOffsetsDoNotOverlap() local
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| H A D | AMDGPUInstructionSelector.cpp | 1268 unsigned Offset0 = OrderedCountIndex << 2; in selectDSOrderedIntrinsic() local
3792 bool AMDGPUInstructionSelector::isDSOffset2Legal(Register Base, int64_t Offset0, in isDSOffset2Legal()
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| H A D | SIISelLowering.cpp | 6846 unsigned Offset0 = OrderedCountIndex << 2; in LowerINTRINSIC_W_CHAIN() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 15264 const APInt &Offset0 = CN->getAPIntValue(); in CombineToPreIndexedLoadStore() local
17384 int64_t Offset0 = LoadNodes[0].OffsetFromBase; in tryStoreMergeOfLoads() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 7764 bool Offset0 = false, Offset1 = false; in getFauxShuffleMask() local
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