| /llvm-project/llvm/unittests/DebugInfo/DWARF/ |
| H A D | DWARFListTableTest.cpp | 94 std::optional<uint64_t> Offset0 = Header.getOffsetEntry(Extractor, 0); in TEST() local
|
| /llvm-project/llvm/unittests/CodeGen/ |
| H A D | SelectionDAGAddressAnalysisTest.cpp | 157 TypeSize Offset0 = TypeSize::getFixed(0); TEST_F() local
278 TypeSize Offset0 = TypeSize::getFixed(0); TEST_F() local
319 TypeSize Offset0 = TypeSize::getFixed(0); TEST_F() local
353 TypeSize Offset0 = TypeSize::getFixed(0); TEST_F() local
[all...] |
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMHazardRecognizer.cpp | 192 int64_t Offset0 = 0; getHazardType() local
|
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 393 int64_t Offset0; apply() local
|
| H A D | HexagonISelLoweringHVX.cpp | 2196 SDValue Offset0 = DAG.getTargetConstant(0, dl, ty(Base)); LowerHvxMaskedOp() local
|
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 1247 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size)) in SelectDS64Bit4ByteAligned() argument
1153 isDSOffset2Legal(SDValue Base,unsigned Offset0,unsigned Offset1,unsigned Size) const isDSOffset2Legal() argument
1253 SelectDS128Bit8ByteAligned(SDValue Addr,SDValue & Base,SDValue & Offset0,SDValue & Offset1) const SelectDS128Bit8ByteAligned() argument
1259 SelectDSReadWrite2(SDValue Addr,SDValue & Base,SDValue & Offset0,SDValue & Offset1,unsigned Size) const SelectDSReadWrite2() argument
[all...] |
| H A D | SIInstrInfo.cpp | 234 areLoadsFromSameBasePtr(SDNode * Load0,SDNode * Load1,int64_t & Offset0,int64_t & Offset1) const areLoadsFromSameBasePtr() argument
397 unsigned Offset0 = Offset0Op->getImm() & 0xff; getMemOperandsWithOffsetWidth() local
596 shouldScheduleLoadsNear(SDNode * Load0,SDNode * Load1,int64_t Offset0,int64_t Offset1,unsigned NumLoads) const shouldScheduleLoadsNear() argument
3702 int64_t Offset0, Offset1; checkInstOffsetsDoNotOverlap() local
[all...] |
| H A D | AMDGPUInstructionSelector.cpp | 1600 unsigned Offset0 = OrderedCountIndex << 2; selectDSOrderedIntrinsic() local
4710 isDSOffset2Legal(Register Base,int64_t Offset0,int64_t Offset1,unsigned Size) const isDSOffset2Legal() argument
|
| H A D | SIISelLowering.cpp | 8877 unsigned Offset0 = OrderedCountIndex << 2; LowerINTRINSIC_W_CHAIN() local
|
| /llvm-project/llvm/lib/Analysis/ |
| H A D | ConstantFolding.cpp | 1249 APInt Offset0(IndexWidth, 0); ConstantFoldCompareInstOperands() local
|
| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 18584 const APInt &Offset0 = CN->getAPIntValue(); CombineToPreIndexedLoadStore() local
20859 int64_t Offset0 = LoadNodes[0].OffsetFromBase; tryStoreMergeOfLoads() local
[all...] |
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 6120 bool Offset0 = false, Offset1 = false; getFauxShuffleMask() local
[all...] |