| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMHazardRecognizer.cpp | 192 int64_t Offset0 = 0; in getHazardType() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 397 int64_t Offset0; apply() local
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| H A D | HexagonISelLoweringHVX.cpp | 2196 SDValue Offset0 = DAG.getTargetConstant(0, dl, ty(Base)); in LowerHvxMaskedOp() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 1129 isDSOffset2Legal(SDValue Base,unsigned Offset0,unsigned Offset1,unsigned Size) const isDSOffset2Legal() argument
1223 SelectDS64Bit4ByteAligned(SDValue Addr,SDValue & Base,SDValue & Offset0,SDValue & Offset1) const SelectDS64Bit4ByteAligned() argument
1229 SelectDS128Bit8ByteAligned(SDValue Addr,SDValue & Base,SDValue & Offset0,SDValue & Offset1) const SelectDS128Bit8ByteAligned() argument
1235 SelectDSReadWrite2(SDValue Addr,SDValue & Base,SDValue & Offset0,SDValue & Offset1,unsigned Size) const SelectDSReadWrite2() argument
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| H A D | SIInstrInfo.cpp | 236 areLoadsFromSameBasePtr(SDNode * Load0,SDNode * Load1,int64_t & Offset0,int64_t & Offset1) const areLoadsFromSameBasePtr() argument
399 unsigned Offset0 = Offset0Op->getImm() & 0xff; getMemOperandsWithOffsetWidth() local
596 shouldScheduleLoadsNear(SDNode * Load0,SDNode * Load1,int64_t Offset0,int64_t Offset1,unsigned NumLoads) const shouldScheduleLoadsNear() argument
3649 int64_t Offset0, Offset1; checkInstOffsetsDoNotOverlap() local
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| H A D | AMDGPUInstructionSelector.cpp | 1610 unsigned Offset0 = OrderedCountIndex << 2; selectDSOrderedIntrinsic() local
4739 isDSOffset2Legal(Register Base,int64_t Offset0,int64_t Offset1,unsigned Size) const isDSOffset2Legal() argument
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| H A D | SIISelLowering.cpp | 8437 unsigned Offset0 = OrderedCountIndex << 2; LowerINTRINSIC_W_CHAIN() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ConstantFolding.cpp | 1264 APInt Offset0(IndexWidth, 0); ConstantFoldCompareInstOperands() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 18293 const APInt &Offset0 = CN->getAPIntValue(); CombineToPreIndexedLoadStore() local
20568 int64_t Offset0 = LoadNodes[0].OffsetFromBase; tryStoreMergeOfLoads() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 5949 bool Offset0 = false, Offset1 = false; getFauxShuffleMask() local
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