1 /* Interrupt numbers and hardware vectors. */ 2 3 #ifndef _INTERRUPT_H 4 #define _INTERRUPT_H 5 6 #if defined(__i386__) 7 8 /* 8259A interrupt controller ports. */ 9 #define INT_CTL 0x20 /* I/O port for interrupt controller */ 10 #define INT_CTLMASK 0x21 /* setting bits in this port disables ints */ 11 #define INT2_CTL 0xA0 /* I/O port for second interrupt controller */ 12 #define INT2_CTLMASK 0xA1 /* setting bits in this port disables ints */ 13 14 /* Magic numbers for interrupt controller. */ 15 #define END_OF_INT 0x20 /* code used to re-enable after an interrupt */ 16 17 #define IRQ0_VECTOR 0x50 /* nice vectors to relocate IRQ0-7 to */ 18 #define IRQ8_VECTOR 0x70 /* no need to move IRQ8-15 */ 19 20 /* Interrupt vectors defined/reserved by processor. */ 21 #define DIVIDE_VECTOR 0 /* divide error */ 22 #define DEBUG_VECTOR 1 /* single step (trace) */ 23 #define NMI_VECTOR 2 /* non-maskable interrupt */ 24 #define BREAKPOINT_VECTOR 3 /* software breakpoint */ 25 #define OVERFLOW_VECTOR 4 /* from INTO */ 26 27 /* Fixed system call vector. */ 28 #define KERN_CALL_VECTOR_ORIG 32 /* system calls are made with int SYSVEC */ 29 #define IPC_VECTOR_ORIG 33 /* interrupt vector for ipc */ 30 #define KERN_CALL_VECTOR_UM 34 /* user-mapped equivalent */ 31 #define IPC_VECTOR_UM 35 /* user-mapped equivalent */ 32 33 /* Hardware interrupt numbers. */ 34 #ifndef USE_APIC 35 #define NR_IRQ_VECTORS 16 36 #else 37 #define NR_IRQ_VECTORS 64 38 #endif 39 #define CLOCK_IRQ 0 40 #define KEYBOARD_IRQ 1 41 #define CASCADE_IRQ 2 /* cascade enable for 2nd AT controller */ 42 #define ETHER_IRQ 3 /* default ethernet interrupt vector */ 43 #define SECONDARY_IRQ 3 /* RS232 interrupt vector for port 2 */ 44 #define RS232_IRQ 4 /* RS232 interrupt vector for port 1 */ 45 #define XT_WINI_IRQ 5 /* xt winchester */ 46 #define FLOPPY_IRQ 6 /* floppy disk */ 47 #define PRINTER_IRQ 7 48 #define SPURIOUS_IRQ 7 49 #define CMOS_CLOCK_IRQ 8 50 #define KBD_AUX_IRQ 12 /* AUX (PS/2 mouse) port in kbd controller */ 51 #define AT_WINI_0_IRQ 14 /* at winchester controller 0 */ 52 #define AT_WINI_1_IRQ 15 /* at winchester controller 1 */ 53 54 #define VECTOR(irq) \ 55 (((irq) < 8 ? IRQ0_VECTOR : IRQ8_VECTOR) + ((irq) & 0x07)) 56 57 #endif /* (CHIP == INTEL) */ 58 59 #endif /* _INTERRUPT_H */ 60