| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetOpcodes.h | 22 #define HANDLE_TARGET_OPCODE(OPC) OPC, argument
23 #define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) IDENT = OPC, argument
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| /llvm-project/llvm/lib/SandboxIR/ |
| H A D | SandboxIR.cpp | |
| /llvm-project/llvm/include/llvm/SandboxIR/ |
| H A D | SandboxIR.h | |
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86LowerTileCopy.cpp | 138 GET_EGPR_IF_ENABLED(OPC) runOnMachineFunction() argument
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| H A D | X86ExpandPseudo.cpp | 267 GET_EGPR_IF_ENABLED(OPC) expandMI() argument
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| H A D | X86DomainReassignment.cpp | 622 GET_EGPR_IF_ENABLED(OPC) initConverters() argument
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| H A D | X86ISelDAGToDAG.cpp | 279 GET_ND_IF_ENABLED(OPC) getAddressOperands() argument
4153 GET_EGPR_IF_ENABLED(OPC) matchBEXTRFromAndImm() argument
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| H A D | X86InstrInfo.cpp | 3408 GET_ND_IF_ENABLED(OPC) getCMovOpcode() argument
4481 GET_EGPR_IF_ENABLED(OPC) getLoadStoreRegOpcode() argument
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| H A D | X86FastISel.cpp | 3049 GET_EGPR_IF_ENABLED(OPC) fastLowerIntrinsicCall() argument
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| H A D | X86ISelLowering.cpp | 36972 GET_EGPR_IF_ENABLED(OPC) EmitInstrWithCustomInserter() argument
[all...] |
| /llvm-project/llvm/lib/IR/ |
| H A D | Instruction.cpp | 1212 HANDLE_TERM_INST(N,OPC,CLASS) getNumSuccessors() argument
1224 HANDLE_TERM_INST(N,OPC,CLASS) getSuccessor() argument
1236 HANDLE_TERM_INST(N,OPC,CLASS) setSuccessor() argument
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| H A D | Value.cpp | 128 #define HANDLE_INST(N, OPC, CLASS) \ in deleteValue() argument
132 #define HANDLE_USER_INST(N, OPC, CLASS) in deleteValue() argument
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| H A D | IntrinsicInst.cpp | 524 VP_PROPERTY_FUNCTIONAL_OPC(OPC) getFunctionalOpcodeForVP() argument
595 VP_PROPERTY_FUNCTIONAL_OPC(OPC) getForOpcode() argument
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| /llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenTarget.cpp | 298 HANDLE_TARGET_OPCODE(OPC) global() argument
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 1660 OPCODE_LMUL_CASE(OPC) isVectorAssociativeAndCommutative() argument
1669 OPCODE_LMUL_MASK_CASE(OPC) isVectorAssociativeAndCommutative() argument
1956 RVV_OPC_LMUL_CASE(OPC,INV) getInverseOpcode() argument
1972 RVV_OPC_LMUL_MASK_CASE(OPC,INV) getInverseOpcode() argument
[all...] |
| /llvm-project/llvm/lib/Target/VE/ |
| H A D | VECustomDAG.cpp | 362 bool hasReductionStartParam(unsigned OPC) { in hasReductionStartParam() argument
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 301 #define STORE_OPCODE(VAR, OPC) VAR = isThumb ? ARM::t2##OPC : ARM::OPC in OpcodeCache() argument
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetTransformInfo.cpp | 588 const int OPC = TLI->InstructionOpcodeToISD(FAdd->getOpcode()); getArithmeticInstrCost() local
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| H A D | SIISelLowering.cpp | 3914 unsigned OPC = AMDGPUISD::TC_RETURN; LowerCall() local
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