1 /* $NetBSD: omap5.h,v 1.1.1.3 2021/11/07 16:49:59 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright 2017 Texas Instruments, Inc. 6 */ 7 #ifndef __DT_BINDINGS_CLK_OMAP5_H 8 #define __DT_BINDINGS_CLK_OMAP5_H 9 10 #define OMAP5_CLKCTRL_OFFSET 0x20 11 #define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET) 12 13 /* mpu clocks */ 14 #define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 15 16 /* dsp clocks */ 17 #define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 18 19 /* abe clocks */ 20 #define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 21 #define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) 22 #define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 23 #define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) 24 #define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) 25 #define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) 26 #define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) 27 #define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) 28 #define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) 29 #define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) 30 #define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) 31 32 /* l3main1 clocks */ 33 #define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 34 35 /* l3main2 clocks */ 36 #define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 37 #define OMAP5_L3_MAIN_2_GPMC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) 38 #define OMAP5_L3_MAIN_2_OCMC_RAM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 39 40 /* ipu clocks */ 41 #define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 42 43 /* dma clocks */ 44 #define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 45 46 /* emif clocks */ 47 #define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 48 #define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 49 #define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) 50 51 /* l4cfg clocks */ 52 #define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 53 #define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) 54 #define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 55 56 /* l3instr clocks */ 57 #define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 58 #define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) 59 60 /* l4per clocks */ 61 #define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) 62 #define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 63 #define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) 64 #define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) 65 #define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) 66 #define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) 67 #define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60) 68 #define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) 69 #define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) 70 #define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) 71 #define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) 72 #define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0) 73 #define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8) 74 #define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0) 75 #define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8) 76 #define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0) 77 #define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) 78 #define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8) 79 #define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100) 80 #define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108) 81 #define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110) 82 #define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118) 83 #define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120) 84 #define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128) 85 #define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140) 86 #define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148) 87 #define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150) 88 #define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158) 89 #define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160) 90 #define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168) 91 #define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) 92 #define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) 93 94 /* l4_secure clocks */ 95 #define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0 96 #define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET) 97 #define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0) 98 #define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8) 99 #define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0) 100 #define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8) 101 #define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0) 102 #define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8) 103 #define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8) 104 105 /* iva clocks */ 106 #define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 107 #define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) 108 109 /* dss clocks */ 110 #define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 111 112 /* gpu clocks */ 113 #define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 114 115 /* l3init clocks */ 116 #define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) 117 #define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 118 #define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) 119 #define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) 120 #define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88) 121 #define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0) 122 #define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8) 123 #define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) 124 125 /* wkupaon clocks */ 126 #define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 127 #define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 128 #define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) 129 #define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) 130 #define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) 131 #define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) 132 133 #endif 134