| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.h | 23 explicit MipsSEDAGToDAGISel(MipsTargetMachine &TM, CodeGenOptLevel OL) in MipsSEDAGToDAGISel() argument
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| H A D | Mips16ISelDAGToDAG.h | 22 explicit Mips16DAGToDAGISel(MipsTargetMachine &TM, CodeGenOptLevel OL) in Mips16DAGToDAGISel()
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| H A D | MipsISelDAGToDAG.h | 35 explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOptLevel OL) in MipsDAGToDAGISel() argument
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| H A D | MipsTargetMachine.cpp | 126 MipsTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT,bool isLittle) MipsTargetMachine() argument
155 MipsebTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) MipsebTargetMachine() argument
165 MipselTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) MipselTargetMachine() argument
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| /llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcTargetMachine.cpp | 103 SparcTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT,bool is64bit) SparcTargetMachine() argument
205 SparcV8TargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) SparcV8TargetMachine() argument
215 SparcV9TargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) SparcV9TargetMachine() argument
225 SparcelTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) SparcelTargetMachine() argument
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| /llvm-project/llvm/unittests/Analysis/ |
| H A D | LoopNestTest.cpp | 98 const Loop &OL = LN.getOutermostLoop(); in TEST() local
196 const Loop &OL = LN.getOutermostLoop(); in TEST() local
280 const Loop &OL = LN.getOutermostLoop(); in TEST() local
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| /llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaTargetMachine.cpp | 50 XtensaTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT,bool IsLittle) XtensaTargetMachine() argument
64 XtensaTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) XtensaTargetMachine() argument
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| /llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 129 NVPTXTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool is64bit) NVPTXTargetMachine() argument
156 NVPTXTargetMachine32(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) NVPTXTargetMachine32() argument
166 NVPTXTargetMachine64(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) NVPTXTargetMachine64() argument
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMTargetMachine.cpp | 224 ARMBaseTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool isLittle) ARMBaseTargetMachine() argument
332 ARMLETargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) ARMLETargetMachine() argument
340 ARMBETargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) ARMBETargetMachine() argument
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| /llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCTargetMachine.cpp | 35 CodeGenOptLevel OL, bool JIT) in ARCTargetMachine() argument
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| /llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430TargetMachine.cpp | 46 MSP430TargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) MSP430TargetMachine() argument
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| /llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreTargetMachine.cpp | 50 XCoreTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) XCoreTargetMachine() argument
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetMachine.cpp | 347 AArch64TargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT,bool LittleEndian) AArch64TargetMachine() argument
478 AArch64leTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) AArch64leTargetMachine() argument
486 AArch64beTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) AArch64beTargetMachine() argument
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetMachine.cpp | 200 computeFSAdditions(StringRef FS,CodeGenOptLevel OL,const Triple & TT) computeFSAdditions() argument
349 PPCTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) PPCTargetMachine() argument
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| /llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRTargetMachine.cpp | 51 AVRTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) AVRTargetMachine() argument
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| /llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYTargetMachine.cpp | 56 CodeGenOptLevel OL, bool JIT) in CSKYTargetMachine() argument
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| /llvm-project/llvm/lib/Target/VE/ |
| H A D | VETargetMachine.cpp | 91 CodeGenOptLevel OL, bool JIT) in VETargetMachine() argument
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| /llvm-project/clang-tools-extra/test/clang-tidy/checkers/modernize/ |
| H A D | use-equals-default.cpp | 4 class OL { class
10 OL::OL() {}; in OL() function in OL
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| /llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVTargetMachine.cpp | 81 SPIRVTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) SPIRVTargetMachine() argument
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600TargetMachine.cpp | 57 R600TargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) R600TargetMachine() argument
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| /llvm-project/clang/tools/clang-fuzzer/handle-llvm/ |
| H A D | handle_llvm.cpp | 76 llvm::OptimizationLevel OL; in RunOptimizationPasses() local
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| /llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kTargetMachine.cpp | 104 M68kTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) M68kTargetMachine() argument
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| /llvm-project/llvm/lib/Target/DirectX/ |
| H A D | DirectXTargetMachine.cpp | 92 DirectXTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) DirectXTargetMachine() argument
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| /llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFTargetMachine.cpp | 71 BPFTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) BPFTargetMachine() argument
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| /llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchTargetMachine.cpp | 90 LoongArchTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) LoongArchTargetMachine() argument
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