Searched defs:NumVecs (Results 1 – 7 of 7) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1247 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectTable()
1369 void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectLoad()
1398 void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs, in SelectPostLoad()
1454 void AArch64DAGToDAGISel::SelectPredicatedLoad(SDNode *N, unsigned NumVecs, in SelectPredicatedLoad()
1487 void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs, in SelectStore()
1507 void AArch64DAGToDAGISel::SelectPredicatedStore(SDNode *N, unsigned NumVecs, in SelectPredicatedStore()
1549 void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs, in SelectPostStore()
1605 void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs, in SelectLoadLane()
1644 void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs, in SelectPostLoadLane()
1699 void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs, in SelectStoreLane()
[all …]
|
| H A D | AArch64ISelLowering.cpp | 14850 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
16333 uint64_t NumVecs = TupleLanes / NumLanes; in PerformDAGCombine() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| H A D | VectorUtils.cpp | 786 unsigned NumVecs) { in createInterleaveMask()
844 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1921 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign()
2068 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) { in isPerfectIncrement()
2073 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD()
2215 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVST()
2370 unsigned NumVecs, in SelectVLDSTLane()
2749 void ARMDAGToDAGISel::SelectMVE_VLD(SDNode *N, unsigned NumVecs, in SelectMVE_VLD()
2912 bool isUpdating, unsigned NumVecs, in SelectVLDDup()
|
| H A D | ARMISelLowering.cpp | 14634 unsigned NumVecs = 0; in CombineBaseUpdate() local
14878 unsigned NumVecs = 0; in PerformMVEVLDCombine() local
14971 unsigned NumVecs = 0; in CombineVLDDUP() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 10310 int NumVecs = 2; in LowerINTRINSIC_WO_CHAIN() local
10560 unsigned NumVecs = VT.getSizeInBits() / 128; in LowerVectorLoad() local
10605 unsigned NumVecs = 2; in LowerVectorStore() local
|
| /netbsd-src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 15363 unsigned NumVecs = 2; in EmitPPCBuiltinExpr() local
|