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Searched defs:NewRC (Results 1 – 24 of 24) sorted by relevance

/llvm-project/llvm/lib/CodeGen/
H A DRegisterCoalescer.h57 const TargetRegisterClass *NewRC = nullptr; variable
H A DCriticalAntiDepBreaker.cpp186 const TargetRegisterClass *NewRC = nullptr; in PrescanInstruction() local
314 const TargetRegisterClass *NewRC = nullptr; in ScanInstruction() local
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H A DMachineRegisterInfo.cpp126 const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC, *MF); in recomputeRegClass() local
75 const TargetRegisterClass *NewRC = constrainRegClass() local
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H A DPeepholeOptimizer.cpp823 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); insertPHI() local
H A DRegisterCoalescer.cpp1382 const TargetRegisterClass *NewRC = CP.getNewRC(); reMaterializeTrivialDef() local
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/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.cpp316 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
/llvm-project/llvm/lib/Analysis/
H A DLazyCallGraph.cpp1659 RefSCC *NewRC = OriginalRC; addSplitFunction() local
1684 RefSCC *NewRC = createRefSCC(*this); addSplitFunction() local
1733 RefSCC *NewRC; addSplitRefRecursiveFunctions() local
1955 RefSCC *NewRC = createRefSCC(*this); buildRefSCCs() local
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/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp356 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
H A DHexagonVLIWPacketizer.cpp361 const TargetRegisterClass *NewRC) { in isNewifiable() argument
H A DHexagonBitSimplify.cpp2654 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0() local
2722 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0() local
H A DHexagonFrameLowering.cpp2198 if (HaveRC == nullptr || HaveRC == NewRC) in optimizeSpillSlots() argument
H A DHexagonConstPropagation.cpp2896 const TargetRegisterClass *NewRC; rewriteHexConstDefs() local
/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRewritePartialRegUses.cpp451 auto *NewRC = getMinSizeReg(RC, SubRegs); rewriteReg() local
H A DSIRegisterInfo.cpp3032 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
H A DSIInstrInfo.cpp2613 const TargetRegisterClass *NewRC = reMaterialize() local
7225 const TargetRegisterClass *NewRC = moveToVALUImpl() local
H A DSIISelLowering.cpp15246 auto *NewRC = TRI->getEquivalentVGPRClass(RC); AdjustInstrPostInstrSelection() local
15261 auto *NewRC = TRI->getEquivalentAGPRClass(RC); AdjustInstrPostInstrSelection() local
/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp384 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.cpp1055 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp882 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h1118 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) shouldCoalesce() argument
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp5090 const TargetRegisterClass *NewRC = transformToImmFormFedByLI() local
/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp7134 auto *NewRC = MRI.constrainRegClass( updateOperandRegConstraints() local
/llvm-project/clang/lib/Sema/
H A DSemaTemplate.cpp8956 const Expr *NewRC = New->getRequiresClause(); TemplateParameterListsAreEqual() local
H A DSemaOverload.cpp1485 Expr *NewRC = New->getTrailingRequiresClause(), IsOverloadOrOverrideImpl() local