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Searched defs:NewN0 (Results 1 – 5 of 5) sorted by relevance

/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp4981 SDValue NewN0 = SimplifySetCC() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp41292 SDValue NewN0 = SimplifyMultipleUseDemandedVectorElts(N0, DemandedLHS, SimplifyDemandedVectorEltsForTargetNode() local
41329 SDValue NewN0 = SimplifyMultipleUseDemandedVectorElts(N0, DemandedLHS, SimplifyDemandedVectorEltsForTargetNode() local
46465 SDValue NewN0 = DAG.getNode(ISD::TRUNCATE, DL, ReducedVT, N0); reduceVMULWidth() local
48755 SDValue NewN0 = TLI.SimplifyMultipleUseDemandedBits(N0, Bits0, Elts0, DAG); combineAnd() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp12738 SDValue NewN0 = DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV.getOperand(0), combineOrOfCZERO() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp14685 SDValue NewN0 = DAG.getLogicalNOT(DL, N0, VT); PerformORCombine_i1() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp19005 SDValue NewN0 = DAG.getNode(N->getOperand(0).getOpcode(), DL, HalfVT, N0); performVectorAddSubExtCombine() local
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