| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 4307 SDValue MulVal = DAG.getNode(N->getOpcode(), DL, VT, N1, MulOper); performMulCombine() local
4312 SDValue MulVal = DAG.getNode(N->getOpcode(), DL, VT, N0, MulOper); performMulCombine() local
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| H A D | AMDGPULegalizerInfo.cpp | 2825 auto MulVal = B.buildFMul(Ty, SrcReg, OneOver2Pi, Flags); legalizeSinCos() local
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| H A D | SIISelLowering.cpp | 11158 SDValue MulVal = DAG.getNode(ISD::FMUL, DL, VT, Arg, OneOver2Pi, Flags); LowerTrig() local
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| /llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSelect.cpp | 3503 fmulByZeroIsZero(Value * MulVal,FastMathFlags FMF,const Instruction * CtxI) const fmulByZeroIsZero() argument
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| H A D | InstCombineCompares.cpp | 6145 processUMulZExtIdiom(ICmpInst & I,Value * MulVal,const APInt * OtherVal,InstCombinerImpl & IC) processUMulZExtIdiom() argument
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| /llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 5706 APInt MulVal = APInt(BitWidth, 1) << ShiftAmt; TryMULWIDECombine() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2583 SDValue MulVal = N.getOperand(0); matchAddressRecursively() local
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 14051 SDValue MulVal = DAG.getNode(ISD::MUL, DL, VT, N1, MulOper); performMULCombine() local
14056 SDValue MulVal = DAG.getNode(ISD::MUL, DL, VT, N0, MulOper); performMULCombine() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 18067 SDValue MulVal = DAG.getNode(ISD::MUL, DL, VT, N1, MulOper); performMulCombine() local
18072 SDValue MulVal = DAG.getNode(ISD::MUL, DL, VT, N0, MulOper); performMulCombine() local
[all...] |
| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 4517 APInt MulVal; visitMUL() local
[all...] |