| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMParallelDSP.cpp | 610 if (Mul0 == Mul1) in CreateParallelPairs() local
144 AddMulPair(MulCandidate * Mul0,MulCandidate * Mul1,bool Exchange=false) AddMulPair() argument
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| /llvm-project/llvm/unittests/Analysis/ |
| H A D | ScalarEvolutionTest.cpp | 264 const SCEV *Mul1 = SE.getMulExpr(Ops1); in TEST_F() local
404 Instruction *Mul1 = BinaryOperator::CreateMul(Trunc, A2, "", EntryBB); in TEST_F() local
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| /llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 570 isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0, in isADDADDMUL() argument
1647 SDValue Mul0, Mul1, Addend0, Addend1; PerformDAGCombine() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 2082 SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp, LowerUDIVREM64() local
2942 SDValue Mul1 = DAG.getNode(ISD::FMUL, SL, VT, X, K1, Flags); lowerFEXP10Unsafe() local
2968 SDValue Mul1 = DAG.getNode(ISD::FMUL, SL, VT, AdjustedX, K1, Flags); lowerFEXP10Unsafe() local
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| H A D | AMDGPULegalizerInfo.cpp | 4537 auto Mul1 = B.buildFMul( emitReciprocalU64() local
5167 auto Mul1 = B.buildFMul(S32, LHS, RCP, Flags); legalizeFDIVFastIntrin() local
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 2102 WeightedLeaf Mul1, Mul2; in balanceSubTree() local
[all...] |
| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 2227 MachineOperand &Mul1 = Prev.getOperand(1); combineFPFusedMultiply() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 28780 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, LowerMULH() local
47543 __anon0268aba8a002(int Mul1, int Mul2, bool isAdd) combineMulSpecial() argument
[all...] |