| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVExpandAtomicPseudoInsts.cpp | 303 Register MaskReg, Register ScratchReg) { in insertMaskedMerge()
334 Register MaskReg = MI.getOperand(4).getReg(); in doMaskedAtomicBinOpExpansion() local
475 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicMinMaxOp() local
573 Register MaskReg, in tryToFoldBNEOnCmpXchgResult()
640 Register MaskReg = IsMasked ? MI.getOperand(5).getReg() : Register(); in expandAtomicCmpXchg() local
690 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicCmpXchg() local
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| /llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchExpandAtomicPseudoInsts.cpp | 221 insertMaskedMerge(const LoongArchInstrInfo * TII,DebugLoc DL,MachineBasicBlock * MBB,Register DestReg,Register OldValReg,Register NewValReg,Register MaskReg,Register ScratchReg) insertMaskedMerge() argument
247 Register MaskReg = MI.getOperand(4).getReg(); doMaskedAtomicBinOpExpansion() local
386 Register MaskReg = MI.getOperand(5).getReg(); expandAtomicMinMaxOp() local
537 Register MaskReg = MI.getOperand(5).getReg(); expandAtomicCmpXchg() local
[all...] |
| /llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 101 emitMask(unsigned AddrReg,unsigned MaskReg,const MCSubtargetInfo & STI) emitMask() argument
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 4810 Register MaskReg = MI.getOperand(2).getReg(); getInstrMapping() local
4819 Register MaskReg = MI.getOperand(2).getReg(); getInstrMapping() local
4837 Register MaskReg = MI.getOperand(2).getReg(); getInstrMapping() local
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| H A D | AMDGPUInstructionSelector.cpp | 1456 const Register MaskReg = I.getOperand(2).getReg(); selectInverseBallot() local
2910 Register MaskReg = I.getOperand(2).getReg(); selectG_PTRMASK() local
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| H A D | SIISelLowering.cpp | 5489 Register MaskReg = MI.getOperand(1).getReg(); EmitInstrWithCustomInserter() local
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 232 Register MaskReg = getMRI()->createGenericVirtualRegister(MaskTy); in buildMaskLowPtrBits() local
|
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 6175 Register MaskReg = MIB.getReg(1); expandPostRAPseudo() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 1481 optimizePTestInstr(MachineInstr * PTest,unsigned MaskReg,unsigned PredReg,const MachineRegisterInfo * MRI) const optimizePTestInstr() argument
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| /llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3115 Register MaskReg = I.getOperand(2).getReg(); select() local
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 12276 Register MaskReg = RegInfo.createVirtualRegister(GPRC); EmitPartwordAtomicBinary() local
13291 Register MaskReg = RegInfo.createVirtualRegister(GPRC); EmitInstrWithCustomInserter() local
[all...] |