| /freebsd-src/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | MathExtras.h | 279 isShiftedMask_32(uint32_t Value,unsigned & MaskIdx,unsigned & MaskLen) isShiftedMask_32() argument
292 isShiftedMask_64(uint64_t Value,unsigned & MaskIdx,unsigned & MaskLen) isShiftedMask_64() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 2067 unsigned MaskIdx, MaskLen; instCombineIntrinsic() local
2111 unsigned MaskIdx, MaskLen; instCombineIntrinsic() local
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| H A D | X86ISelDAGToDAG.cpp | 2135 unsigned MaskIdx, MaskLen; foldMaskAndShiftToScale() local
2234 unsigned MaskIdx, MaskLen; foldMaskedShiftToBEXTR() local
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | APInt.h | 500 /// lowest set bit and \p MaskLen is updated to specify the length of the in isShiftedMask() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 2201 unsigned MaskIdx, MaskLen; performSRLCombine() local
2362 unsigned MaskIdx, MaskLen; performORCombine() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 1086 unsigned MaskLen = SM.Mask.size(); in getOutputSegmentMap() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 728 unsigned LowZBits, MaskLen; SelectShiftedRegisterFromAnd() local
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| H A D | AArch64ISelLowering.cpp | 16403 unsigned MaskIdx, MaskLen; isDesirableToCommuteXorWithShift() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 4057 unsigned MaskIdx, MaskLen; performSrlCombine() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13845 unsigned MaskIdx, MaskLen; isDesirableToCommuteXorWithShift() local
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