| /llvm-project/llvm/unittests/Support/ |
| H A D | MathExtrasTest.cpp | 101 unsigned MaskIdx, MaskLen; in TEST() local
120 unsigned MaskIdx, MaskLen; in TEST() local
[all...] |
| /llvm-project/llvm/include/llvm/Support/ |
| H A D | MathExtras.h | 305 isShiftedMask_32(uint32_t Value,unsigned & MaskIdx,unsigned & MaskLen) isShiftedMask_32() argument
318 isShiftedMask_64(uint64_t Value,unsigned & MaskIdx,unsigned & MaskLen) isShiftedMask_64() argument
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| /llvm-project/llvm/lib/Target/VE/ |
| H A D | VVPISelLowering.cpp | 68 auto MaskIdx = ISD::getVPMaskIdx(Opcode); in lowerToVVP() local
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| /llvm-project/llvm/include/llvm/ADT/ |
| H A D | APInt.h | 502 isShiftedMask(unsigned & MaskIdx,unsigned & MaskLen) isShiftedMask() argument
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 2216 unsigned MaskIdx, MaskLen; instCombineIntrinsic() local
2260 unsigned MaskIdx, MaskLen; instCombineIntrinsic() local
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| H A D | X86ISelDAGToDAG.cpp | 2188 unsigned MaskIdx, MaskLen; foldMaskAndShiftToScale() local
2287 unsigned MaskIdx, MaskLen; foldMaskedShiftToBEXTR() local
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| H A D | X86ISelLowering.cpp | 9655 int MaskIdx = Mask[i]; isShuffleEquivalent() local
9706 int MaskIdx = Mask[i]; isTargetShuffleEquivalent() local
45273 SDValue MaskIdx = DAG.getZExtOrTrunc(Use->getOperand(1), dl, MVT::i8); combineExtractVectorElt() local
[all...] |
| /llvm-project/llvm/lib/CodeGen/ |
| H A D | ComplexDeinterleavingPass.cpp | 499 int MaskIdx = Idx * 2; isInterleavingMask() local
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| /llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 2295 unsigned MaskIdx, MaskLen; performSRLCombine() local
2456 unsigned MaskIdx, MaskLen; performORCombine() local
[all...] |
| /llvm-project/clang/lib/CodeGen/ |
| H A D | CodeGenFunction.cpp | 3044 for (unsigned MaskIdx = 0; emitBoolVecConversion() local
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| /llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 1887 const SDValue &MaskIdx = Op.getOperand(OpIdx + 1); LowerIntrinsic() local
|
| /llvm-project/llvm/unittests/ADT/ |
| H A D | APIntTest.cpp | 1796 unsigned MaskIdx, MaskLen; TEST() local
[all...] |
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 2310 if (MaskIdx == (0x00010203 | MaskUnd)) { in LowerVECTOR_SHUFFLE() local
[all...] |
| /llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 313 auto MaskIdx = [&](Value *Idx) { foldCmpLoadFromIndexedGlobal() local
|
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 4114 unsigned MaskIdx, MaskLen; performSrlCombine() local
|
| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 2799 int MaskIdx = MaskElt / NewElts; SplitVecRes_VECTOR_SHUFFLE() local
|
| H A D | DAGCombiner.cpp | 26732 if (auto MaskIdx = ISD::getVPMaskIdx(N->getOpcode())) visitVPOp() local
[all...] |
| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 5318 __anon17a3f42a0e02(const auto &MaskIdx) lowerVECTOR_SHUFFLE() argument
11245 auto MaskIdx = ISD::getVPMaskIdx(Op.getOpcode()); lowerVPOp() local
|
| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 11803 SDValue MaskIdx = MaskSource.getOperand(1); ReconstructShuffleWithRuntimeMask() local
17326 unsigned MaskIdx, MaskLen; isDesirableToCommuteXorWithShift() local
[all...] |
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13865 unsigned MaskIdx, MaskLen; isDesirableToCommuteXorWithShift() local
|