| /freebsd-src/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | MathExtras.h | 278 isShiftedMask_32(uint32_t Value,unsigned & MaskIdx,unsigned & MaskLen) isShiftedMask_32() argument
291 isShiftedMask_64(uint64_t Value,unsigned & MaskIdx,unsigned & MaskLen) isShiftedMask_64() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VVPISelLowering.cpp | 68 auto MaskIdx = ISD::getVPMaskIdx(Opcode); in lowerToVVP() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 2067 unsigned MaskIdx, MaskLen; instCombineIntrinsic() local
2111 unsigned MaskIdx, MaskLen; instCombineIntrinsic() local
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| H A D | X86ISelDAGToDAG.cpp | 2135 unsigned MaskIdx, MaskLen; foldMaskAndShiftToScale() local
2234 unsigned MaskIdx, MaskLen; foldMaskedShiftToBEXTR() local
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| H A D | X86ISelLowering.cpp | 9489 int MaskIdx = Mask[i]; isShuffleEquivalent() local
9540 int MaskIdx = Mask[i]; isTargetShuffleEquivalent() local
44281 SDValue MaskIdx = DAG.getZExtOrTrunc(Use->getOperand(1), dl, MVT::i8); combineExtractVectorElt() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | APInt.h | 500 isShiftedMask(unsigned & MaskIdx,unsigned & MaskLen) isShiftedMask() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ComplexDeinterleavingPass.cpp | 499 int MaskIdx = Idx * 2; in isInterleavingMask() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 2201 unsigned MaskIdx, MaskLen; performSRLCombine() local
2362 unsigned MaskIdx, MaskLen; performORCombine() local
[all...] |
| /freebsd-src/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CodeGenFunction.cpp | 2966 for (unsigned MaskIdx = 0; emitBoolVecConversion() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 1871 const SDValue &MaskIdx = Op.getOperand(OpIdx + 1); LowerIntrinsic() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 2288 uint64_t MaskIdx = 0; LowerVECTOR_SHUFFLE() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 309 auto MaskIdx = [&](Value *Idx) { foldCmpLoadFromIndexedGlobal() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 4057 unsigned MaskIdx, MaskLen; performSrlCombine() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 2665 int MaskIdx = MaskElt / NewElts; SplitVecRes_VECTOR_SHUFFLE() local
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| H A D | DAGCombiner.cpp | 26403 if (auto MaskIdx = ISD::getVPMaskIdx(N->getOpcode())) visitVPOp() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 4934 __anonbba6e2090b02(const auto &MaskIdx) lowerVECTOR_SHUFFLE() argument
10474 auto MaskIdx = ISD::getVPMaskIdx(Op.getOpcode()); lowerVPOp() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 10986 SDValue MaskIdx = MaskSource.getOperand(1); ReconstructShuffleWithRuntimeMask() local
16403 unsigned MaskIdx, MaskLen; isDesirableToCommuteXorWithShift() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13845 unsigned MaskIdx, MaskLen; isDesirableToCommuteXorWithShift() local
|