| /llvm-project/llvm/lib/CodeGen/ |
| H A D | DetectDeadLanes.cpp | 112 Register MOReg = MO.getReg(); in addUsedLanesOnOperand() local
296 Register MOReg = MO.getReg(); in determineInitialDefinedLanes() local
445 Register MOReg = MO.getReg(); in isUndefInput() local
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| H A D | LiveVariables.cpp | 536 Register MOReg = MO.getReg(); in runOnInstr() local
506 Register MOReg = MO.getReg(); runOnInstr() local
524 for (unsigned MOReg : UseRegs) { runOnInstr() local
[all...] |
| H A D | TwoAddressInstructionPass.cpp | 891 Register MOReg = MO.getReg(); rescheduleMIBelowKill() local
934 Register MOReg = MO.getReg(); rescheduleMIBelowKill() local
1071 Register MOReg = MO.getReg(); rescheduleKillAboveMI() local
1108 Register MOReg = MO.getReg(); rescheduleKillAboveMI() local
1127 for (Register MOReg : OtherDefs) { rescheduleKillAboveMI() local
[all...] |
| H A D | MachineInstrBundle.cpp | 349 Register MOReg = MO.getReg(); in AnalyzePhysRegInBundle() local
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| H A D | MachineCSE.cpp | 393 Register MOReg = MO.getReg(); PhysRegDefsReach() local
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| H A D | MachineInstr.cpp | 1062 Register MOReg = MO.getReg(); findRegisterUseOperandIdx() local
1116 Register MOReg = MO.getReg(); findRegisterDefOperandIdx() local
2088 Register MOReg = MO.getReg(); addRegisterDead() local
[all...] |
| H A D | TargetInstrInfo.cpp | 1665 const MachineOperand &MOReg = MI.getOperand(OpIdx); getRegSequenceInputs() local
1690 const MachineOperand &MOReg = MI.getOperand(1); getExtractSubregInputs() local
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| H A D | MachineLICM.cpp | 1170 Register MOReg = MO.getReg(); HasHighOperandLatency() local
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCTLSDynamicCall.cpp | 204 if (RegInfo.hasOneDef(MOReg)) { in processBlock() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeVGPRLiveRange.cpp | 238 Register MOReg = MO.getReg(); collectCandidateRegisters() local
364 Register MOReg = MO.getReg(); collectWaterfallCandidateRegisters() local
[all...] |
| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZElimCompare.cpp | 143 if (Register MOReg = MO.getReg()) { in getRegReferences() local
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| /llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcAsmPrinter.cpp | 443 Register MOReg = MO.getReg(); PrintAsmOperand() local
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 565 Register MOReg = MO.getReg(); restoreLatency() local
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 5491 if (!MOReg->isUndef()) in getExtractSubregLikeInputs() local
5465 const MachineOperand *MOReg = &MI.getOperand(1); getRegSequenceLikeInputs() local
[all...] |