| /netbsd-src/external/gpl3/binutils.old/dist/include/opcode/ |
| H A D | arc.h | 482 #define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16)) argument
483 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F)) argument
484 #define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP)) argument
486 #define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP)) argument
487 #define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62)) argument
488 #define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62)) argument
489 #define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62)) argument
490 #define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62)) argument
491 #define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62)) argument
492 #define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62)) argument
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| /netbsd-src/external/gpl3/binutils/dist/include/opcode/ |
| H A D | arc.h | 482 #define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16)) argument
483 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F)) argument
484 #define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP)) argument
486 #define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP)) argument
487 #define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62)) argument
488 #define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62)) argument
489 #define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62)) argument
490 #define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62)) argument
491 #define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62)) argument
492 #define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62)) argument
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | LiveRegUnits.cpp | 42 for (const MachineOperand &MOP : phys_regs_and_masks(MI)) { in stepBackward() local
53 for (const MachineOperand &MOP : phys_regs_and_masks(MI)) { in stepBackward() local
62 for (const MachineOperand &MOP : phys_regs_and_masks(MI)) { in accumulate() local
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| H A D | LivePhysRegs.cpp | 46 for (const MachineOperand &MOP : phys_regs_and_masks(MI)) { in removeDefs() local
59 for (const MachineOperand &MOP : phys_regs_and_masks(MI)) { in addUses() local
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| H A D | MachineCSE.cpp | 301 for (const auto &MOP : llvm::enumerate(MI->operands())) { in hasLivePhysRegDefUses() local
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| H A D | MachineVerifier.cpp | 2243 for (const MachineOperand &MOP : MI->uses()) { in checkLiveness() local
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| /netbsd-src/external/gpl3/binutils.old/dist/opcodes/ |
| H A D | arc-ext-tbl.h | 58 #define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \ argument
72 #define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ argument
76 #define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ argument
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| /netbsd-src/external/gpl3/binutils/dist/opcodes/ |
| H A D | arc-ext-tbl.h | 58 #define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \ argument
72 #define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ argument
76 #define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ argument
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64LoadStoreOptimizer.cpp | 822 bool isDef = any_of(I.operands(), [DefReg, TRI](MachineOperand &MOP) { in forAllMIsUntilDef()
837 for (const MachineOperand &MOP : phys_regs_and_masks(MI)) in updateDefinedRegisters() local
841 for (const MachineOperand &MOP : phys_regs_and_masks(MI)) in updateDefinedRegisters() local
887 for (auto &MOP : MI.operands()) { in mergePairedInsns() local
901 for (auto &MOP : MI.operands()) { in mergePairedInsns() local
924 [this, &RenameReg](const MachineOperand &MOP) { in mergePairedInsns()
1072 for (const MachineOperand &MOP : phys_regs_and_masks(*I)) in mergePairedInsns() local
1365 [TRI, RegToRename](const MachineOperand &MOP) { in canRenameUpToDef()
1373 auto canRenameMOP = [TRI](const MachineOperand &MOP) { in canRenameUpToDef()
1431 for (auto &MOP : MI.operands()) { in canRenameUpToDef() local
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| H A D | AArch64ExpandPseudoInsts.cpp | 678 auto MOP = MI.getOperand(RegMaskStartIdx); in expandCALL_RVMARKER() local
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| H A D | AArch64InstrInfo.cpp | 6984 for (const MachineOperand &MOP : MI.operands()) { in getOutliningType() local
7018 for (const MachineOperand &MOP : MI.operands()) { in getOutliningType() local
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| /netbsd-src/sys/arch/i386/i386/ |
| H A D | cpu_in_cksum.S | 93 #define MOP \ macro
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 6153 for (const MachineOperand &MOP : MI.operands()) { in getOutliningType() local
6167 for (const MachineOperand &MOP : MI.operands()) { in getOutliningType() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 2687 bool CombinerHelper::matchConstantOp(const MachineOperand &MOP, int64_t C) { in matchConstantOp()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 9033 for (const MachineOperand &MOP : MI.operands()) in getOutliningType() local
|