1 /* Definitions of target machine for GNU compiler. MIPS version. 2 Copyright (C) 1989-2022 Free Software Foundation, Inc. 3 Contributed by A. Lichnewsky (lich@inria.inria.fr). 4 Changed by Michael Meissner (meissner@osf.org). 5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and 6 Brendan Eich (brendan@microunity.com). 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 GCC is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with GCC; see the file COPYING3. If not see 22 <http://www.gnu.org/licenses/>. */ 23 24 25 #include "config/vxworks-dummy.h" 26 27 #ifdef GENERATOR_FILE 28 /* This is used in some insn conditions, so needs to be declared, but 29 does not need to be defined. */ 30 extern int target_flags_explicit; 31 #endif 32 33 /* MIPS external variables defined in mips.cc. */ 34 35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32), 36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended 37 to work on a 64-bit machine. */ 38 39 #define ABI_32 0 40 #define ABI_N32 1 41 #define ABI_64 2 42 #define ABI_EABI 3 43 #define ABI_O64 4 44 45 enum mips_isa { 46 MIPS_ISA_MIPS1 = 1, 47 MIPS_ISA_MIPS2 = 2, 48 MIPS_ISA_MIPS3 = 3, 49 MIPS_ISA_MIPS4 = 4, 50 MIPS_ISA_MIPS32 = 32, 51 MIPS_ISA_MIPS32R2 = 33, 52 MIPS_ISA_MIPS32R3 = 34, 53 MIPS_ISA_MIPS32R5 = 36, 54 MIPS_ISA_MIPS32R6 = 37, 55 MIPS_ISA_MIPS64 = 64, 56 MIPS_ISA_MIPS64R2 = 65, 57 MIPS_ISA_MIPS64R3 = 66, 58 MIPS_ISA_MIPS64R5 = 68, 59 MIPS_ISA_MIPS64R6 = 69 60 }; 61 62 /* Masks that affect tuning. 63 64 PTF_AVOID_BRANCHLIKELY_SPEED 65 Set if it is usually not profitable to use branch-likely instructions 66 for this target when optimizing code for speed, typically because 67 the branches are always predicted taken and so incur a large overhead 68 when not taken. 69 70 PTF_AVOID_BRANCHLIKELY_SIZE 71 As above but when optimizing for size. 72 73 PTF_AVOID_BRANCHLIKELY_ALWAYS 74 As above but regardless of whether we optimize for speed or size. 75 76 PTF_AVOID_IMADD 77 Set if it is usually not profitable to use the integer MADD or MSUB 78 instructions because of the overhead of getting the result out of 79 the HI/LO registers. */ 80 81 #define PTF_AVOID_BRANCHLIKELY_SPEED 0x1 82 #define PTF_AVOID_BRANCHLIKELY_SIZE 0x2 83 #define PTF_AVOID_BRANCHLIKELY_ALWAYS (PTF_AVOID_BRANCHLIKELY_SPEED | \ 84 PTF_AVOID_BRANCHLIKELY_SIZE) 85 #define PTF_AVOID_IMADD 0x4 86 87 /* Information about one recognized processor. Defined here for the 88 benefit of TARGET_CPU_CPP_BUILTINS. */ 89 struct mips_cpu_info { 90 /* The 'canonical' name of the processor as far as GCC is concerned. 91 It's typically a manufacturer's prefix followed by a numerical 92 designation. It should be lowercase. */ 93 const char *name; 94 95 /* The internal processor number that most closely matches this 96 entry. Several processors can have the same value, if there's no 97 difference between them from GCC's point of view. */ 98 enum processor cpu; 99 100 /* The ISA level that the processor implements. */ 101 enum mips_isa isa; 102 103 /* A mask of PTF_* values. */ 104 unsigned int tune_flags; 105 }; 106 107 #include "config/mips/mips-opts.h" 108 109 /* Macros to silence warnings about numbers being signed in traditional 110 C and unsigned in ISO C when compiled on 32-bit hosts. */ 111 112 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */ 113 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */ 114 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */ 115 116 117 /* Run-time compilation parameters selecting different hardware subsets. */ 118 119 /* True if we are generating position-independent VxWorks RTP code. */ 120 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic) 121 122 /* Compact branches must not be used if the user either selects the 123 'never' policy or the 'optimal' policy on a core that lacks 124 compact branch instructions. */ 125 #define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER \ 126 || (mips_cb == MIPS_CB_OPTIMAL \ 127 && !ISA_HAS_COMPACT_BRANCHES)) 128 129 /* Compact branches may be used if the user either selects the 130 'always' policy or the 'optimal' policy on a core that supports 131 compact branch instructions. */ 132 #define TARGET_CB_MAYBE (TARGET_CB_ALWAYS \ 133 || (mips_cb == MIPS_CB_OPTIMAL \ 134 && ISA_HAS_COMPACT_BRANCHES)) 135 136 /* Compact branches must always be generated if the user selects 137 the 'always' policy or the 'optimal' policy om a core that 138 lacks delay slot branch instructions. */ 139 #define TARGET_CB_ALWAYS (mips_cb == MIPS_CB_ALWAYS \ 140 || (mips_cb == MIPS_CB_OPTIMAL \ 141 && !ISA_HAS_DELAY_SLOTS)) 142 143 /* Special handling for JRC that exists in microMIPSR3 as well as R6 144 ISAs with full compact branch support. */ 145 #define ISA_HAS_JRC ((ISA_HAS_COMPACT_BRANCHES \ 146 || TARGET_MICROMIPS) \ 147 && mips_cb != MIPS_CB_NEVER) 148 149 /* True if the output file is marked as ".abicalls; .option pic0" 150 (-call_nonpic). */ 151 #define TARGET_ABICALLS_PIC0 \ 152 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT) 153 154 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */ 155 #define TARGET_ABICALLS_PIC2 \ 156 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0) 157 158 /* True if the call patterns should be split into a jalr followed by 159 an instruction to restore $gp. It is only safe to split the load 160 from the call when every use of $gp is explicit. 161 162 See mips_must_initialize_gp_p for details about how we manage the 163 global pointer. */ 164 165 #define TARGET_SPLIT_CALLS \ 166 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed) 167 168 /* True if we're generating a form of -mabicalls in which we can use 169 operators like %hi and %lo to refer to locally-binding symbols. 170 We can only do this for -mno-shared, and only then if we can use 171 relocation operations instead of assembly macros. It isn't really 172 worth using absolute sequences for 64-bit symbols because GOT 173 accesses are so much shorter. */ 174 175 #define TARGET_ABSOLUTE_ABICALLS \ 176 (TARGET_ABICALLS \ 177 && !TARGET_SHARED \ 178 && TARGET_EXPLICIT_RELOCS \ 179 && !ABI_HAS_64BIT_SYMBOLS) 180 181 /* True if we can optimize sibling calls. For simplicity, we only 182 handle cases in which call_insn_operand will reject invalid 183 sibcall addresses. There are two cases in which this isn't true: 184 185 - TARGET_MIPS16. call_insn_operand accepts constant addresses 186 but there is no direct jump instruction. It isn't worth 187 using sibling calls in this case anyway; they would usually 188 be longer than normal calls. 189 190 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand 191 accepts global constants, but all sibcalls must be indirect. */ 192 #define TARGET_SIBCALLS \ 193 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS)) 194 195 /* True if we need to use a global offset table to access some symbols. */ 196 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC) 197 198 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */ 199 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI) 200 201 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */ 202 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP) 203 204 /* True if we should use .cprestore to store to the cprestore slot. 205 206 We continue to use .cprestore for explicit-reloc code so that JALs 207 inside inline asms will work correctly. */ 208 #define TARGET_CPRESTORE_DIRECTIVE \ 209 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16) 210 211 /* True if we can use the J and JAL instructions. */ 212 #define TARGET_ABSOLUTE_JUMPS \ 213 (!flag_pic || TARGET_ABSOLUTE_ABICALLS) 214 215 /* True if indirect calls must use register class PIC_FN_ADDR_REG. 216 This is true for both the PIC and non-PIC VxWorks RTP modes. */ 217 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP) 218 219 /* True if .gpword or .gpdword should be used for switch tables. */ 220 #define TARGET_GPWORD \ 221 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS) 222 223 /* True if the output must have a writable .eh_frame. 224 See ASM_PREFERRED_EH_DATA_FORMAT for details. */ 225 #ifdef HAVE_LD_PERSONALITY_RELAXATION 226 #define TARGET_WRITABLE_EH_FRAME 0 227 #else 228 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED) 229 #endif 230 231 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */ 232 #ifdef HAVE_AS_DSPR1_MULT 233 #define ISA_HAS_DSP_MULT ISA_HAS_DSP 234 #else 235 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2 236 #endif 237 238 /* ISA has LSA available. */ 239 #define ISA_HAS_LSA (mips_isa_rev >= 6 || ISA_HAS_MSA) 240 241 /* ISA has DLSA available. */ 242 #define ISA_HAS_DLSA (TARGET_64BIT \ 243 && (mips_isa_rev >= 6 \ 244 || ISA_HAS_MSA)) 245 246 /* ISA load/store instructions can handle unaligned address */ 247 #define ISA_HAS_UNALIGNED_ACCESS (TARGET_UNALIGNED_ACCESS \ 248 && (mips_isa_rev >= 6)) 249 250 /* The ISA compression flags that are currently in effect. */ 251 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS)) 252 253 /* Generate mips16 code */ 254 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0) 255 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */ 256 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= MIPS_ISA_MIPS32) 257 /* Generate mips16e register save/restore sequences. */ 258 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32) 259 260 /* True if we're generating a form of MIPS16 code in which general 261 text loads are allowed. */ 262 #define TARGET_MIPS16_TEXT_LOADS \ 263 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES) 264 265 /* True if we're generating a form of MIPS16 code in which PC-relative 266 loads are allowed. */ 267 #define TARGET_MIPS16_PCREL_LOADS \ 268 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL) 269 270 /* Generic ISA defines. */ 271 #define ISA_MIPS1 (mips_isa == MIPS_ISA_MIPS1) 272 #define ISA_MIPS2 (mips_isa == MIPS_ISA_MIPS2) 273 #define ISA_MIPS3 (mips_isa == MIPS_ISA_MIPS3) 274 #define ISA_MIPS4 (mips_isa == MIPS_ISA_MIPS4) 275 #define ISA_MIPS32 (mips_isa == MIPS_ISA_MIPS32) 276 #define ISA_MIPS32R2 (mips_isa == MIPS_ISA_MIPS32R2) 277 #define ISA_MIPS32R3 (mips_isa == MIPS_ISA_MIPS32R3) 278 #define ISA_MIPS32R5 (mips_isa == MIPS_ISA_MIPS32R5) 279 #define ISA_MIPS32R6 (mips_isa == MIPS_ISA_MIPS32R6) 280 #define ISA_MIPS64 (mips_isa == MIPS_ISA_MIPS64) 281 #define ISA_MIPS64R2 (mips_isa == MIPS_ISA_MIPS64R2) 282 #define ISA_MIPS64R3 (mips_isa == MIPS_ISA_MIPS64R3) 283 #define ISA_MIPS64R5 (mips_isa == MIPS_ISA_MIPS64R5) 284 #define ISA_MIPS64R6 (mips_isa == MIPS_ISA_MIPS64R6) 285 286 /* Architecture target defines. */ 287 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E) 288 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) 289 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) 290 #define TARGET_GS464 (mips_arch == PROCESSOR_GS464) 291 #define TARGET_GS464E (mips_arch == PROCESSOR_GS464E) 292 #define TARGET_GS264E (mips_arch == PROCESSOR_GS264E) 293 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) 294 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) 295 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) 296 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130) 297 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400) 298 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500) 299 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900) 300 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000) 301 #define TARGET_MIPS8000 (mips_arch == PROCESSOR_R8000) 302 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000) 303 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \ 304 || mips_arch == PROCESSOR_OCTEON2 \ 305 || mips_arch == PROCESSOR_OCTEON3) 306 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \ 307 || mips_arch == PROCESSOR_OCTEON3) 308 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \ 309 || mips_arch == PROCESSOR_SB1A) 310 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000) 311 #define TARGET_XLP (mips_arch == PROCESSOR_XLP) 312 313 /* Scheduling target defines. */ 314 #define TUNE_20KC (mips_tune == PROCESSOR_20KC) 315 #define TUNE_24K (mips_tune == PROCESSOR_24KC \ 316 || mips_tune == PROCESSOR_24KF2_1 \ 317 || mips_tune == PROCESSOR_24KF1_1) 318 #define TUNE_74K (mips_tune == PROCESSOR_74KC \ 319 || mips_tune == PROCESSOR_74KF2_1 \ 320 || mips_tune == PROCESSOR_74KF1_1 \ 321 || mips_tune == PROCESSOR_74KF3_2) 322 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ 323 || mips_tune == PROCESSOR_LOONGSON_2F) 324 #define TUNE_GS464 (mips_tune == PROCESSOR_GS464) 325 #define TUNE_GS464E (mips_tune == PROCESSOR_GS464E) 326 #define TUNE_GS264E (mips_tune == PROCESSOR_GS264E) 327 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) 328 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) 329 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) 330 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120) 331 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130) 332 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000) 333 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400) 334 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500) 335 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000) 336 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000) 337 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000) 338 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \ 339 || mips_tune == PROCESSOR_OCTEON2 \ 340 || mips_tune == PROCESSOR_OCTEON3) 341 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \ 342 || mips_tune == PROCESSOR_SB1A) 343 #define TUNE_P5600 (mips_tune == PROCESSOR_P5600) 344 #define TUNE_I6400 (mips_tune == PROCESSOR_I6400) 345 #define TUNE_P6600 (mips_tune == PROCESSOR_P6600) 346 347 /* True if the pre-reload scheduler should try to create chains of 348 multiply-add or multiply-subtract instructions. For example, 349 suppose we have: 350 351 t1 = a * b 352 t2 = t1 + c * d 353 t3 = e * f 354 t4 = t3 - g * h 355 356 t1 will have a higher priority than t2 and t3 will have a higher 357 priority than t4. However, before reload, there is no dependence 358 between t1 and t3, and they can often have similar priorities. 359 The scheduler will then tend to prefer: 360 361 t1 = a * b 362 t3 = e * f 363 t2 = t1 + c * d 364 t4 = t3 - g * h 365 366 which stops us from making full use of macc/madd-style instructions. 367 This sort of situation occurs frequently in Fourier transforms and 368 in unrolled loops. 369 370 To counter this, the TUNE_MACC_CHAINS code will reorder the ready 371 queue so that chained multiply-add and multiply-subtract instructions 372 appear ahead of any other instruction that is likely to clobber lo. 373 In the example above, if t2 and t3 become ready at the same time, 374 the code ensures that t2 is scheduled first. 375 376 Multiply-accumulate instructions are a bigger win for some targets 377 than others, so this macro is defined on an opt-in basis. */ 378 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \ 379 || TUNE_MIPS4120 \ 380 || TUNE_MIPS4130 \ 381 || TUNE_24K \ 382 || TUNE_P5600) 383 384 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64) 385 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64) 386 387 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is 388 directly accessible, while the command-line options select 389 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI 390 in use. */ 391 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16) 392 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16) 393 394 /* TARGET_FLOAT64 represents -mfp64 and TARGET_FLOATXX represents 395 -mfpxx, derive TARGET_FLOAT32 to represent -mfp32. */ 396 #define TARGET_FLOAT32 (!TARGET_FLOAT64 && !TARGET_FLOATXX) 397 398 /* TARGET_O32_FP64A_ABI represents all the conditions that form the 399 o32 FP64A ABI extension (-mabi=32 -mfp64 -mno-odd-spreg). */ 400 #define TARGET_O32_FP64A_ABI (mips_abi == ABI_32 && TARGET_FLOAT64 \ 401 && !TARGET_ODD_SPREG) 402 403 /* False if SC acts as a memory barrier with respect to itself, 404 otherwise a SYNC will be emitted after SC for atomic operations 405 that require ordering between the SC and following loads and 406 stores. It does not tell anything about ordering of loads and 407 stores prior to and following the SC, only about the SC itself and 408 those loads and stores follow it. */ 409 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP) 410 411 /* Define preprocessor macros for the -march and -mtune options. 412 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected 413 processor. If INFO's canonical name is "foo", define PREFIX to 414 be "foo", and define an additional macro PREFIX_FOO. */ 415 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \ 416 do \ 417 { \ 418 char *macro, *p; \ 419 \ 420 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \ 421 for (p = macro; *p != 0; p++) \ 422 if (*p == '+') \ 423 *p = 'P'; \ 424 else \ 425 *p = TOUPPER (*p); \ 426 \ 427 builtin_define (macro); \ 428 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \ 429 free (macro); \ 430 } \ 431 while (0) 432 433 /* Target CPU builtins. */ 434 #define TARGET_CPU_CPP_BUILTINS() \ 435 do \ 436 { \ 437 builtin_assert ("machine=mips"); \ 438 builtin_assert ("cpu=mips"); \ 439 builtin_define ("__mips__"); \ 440 builtin_define ("_mips"); \ 441 \ 442 /* We do this here because __mips is defined below and so we \ 443 can't use builtin_define_std. We don't ever want to define \ 444 "mips" for VxWorks because some of the VxWorks headers \ 445 construct include filenames from a root directory macro, \ 446 an architecture macro and a filename, where the architecture \ 447 macro expands to 'mips'. If we define 'mips' to 1, the \ 448 architecture macro expands to 1 as well. */ \ 449 if (!flag_iso && !TARGET_VXWORKS) \ 450 builtin_define ("mips"); \ 451 \ 452 if (TARGET_64BIT) \ 453 builtin_define ("__mips64"); \ 454 \ 455 /* Treat _R3000 and _R4000 like register-size \ 456 defines, which is how they've historically \ 457 been used. */ \ 458 if (TARGET_64BIT) \ 459 { \ 460 builtin_define_std ("R4000"); \ 461 builtin_define ("_R4000"); \ 462 } \ 463 else \ 464 { \ 465 builtin_define_std ("R3000"); \ 466 builtin_define ("_R3000"); \ 467 } \ 468 \ 469 if (TARGET_FLOAT64) \ 470 builtin_define ("__mips_fpr=64"); \ 471 else if (TARGET_FLOATXX) \ 472 builtin_define ("__mips_fpr=0"); \ 473 else \ 474 builtin_define ("__mips_fpr=32"); \ 475 \ 476 if (mips_base_compression_flags & MASK_MIPS16) \ 477 builtin_define ("__mips16"); \ 478 \ 479 if (TARGET_MIPS3D) \ 480 builtin_define ("__mips3d"); \ 481 \ 482 if (TARGET_SMARTMIPS) \ 483 builtin_define ("__mips_smartmips"); \ 484 \ 485 if (mips_base_compression_flags & MASK_MICROMIPS) \ 486 builtin_define ("__mips_micromips"); \ 487 \ 488 if (TARGET_MCU) \ 489 builtin_define ("__mips_mcu"); \ 490 \ 491 if (TARGET_EVA) \ 492 builtin_define ("__mips_eva"); \ 493 \ 494 if (TARGET_DSP) \ 495 { \ 496 builtin_define ("__mips_dsp"); \ 497 if (TARGET_DSPR2) \ 498 { \ 499 builtin_define ("__mips_dspr2"); \ 500 builtin_define ("__mips_dsp_rev=2"); \ 501 } \ 502 else \ 503 builtin_define ("__mips_dsp_rev=1"); \ 504 } \ 505 \ 506 if (ISA_HAS_MSA) \ 507 { \ 508 builtin_define ("__mips_msa"); \ 509 builtin_define ("__mips_msa_width=128"); \ 510 } \ 511 \ 512 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \ 513 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \ 514 \ 515 if (ISA_MIPS1) \ 516 { \ 517 builtin_define ("__mips=1"); \ 518 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \ 519 } \ 520 else if (ISA_MIPS2) \ 521 { \ 522 builtin_define ("__mips=2"); \ 523 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \ 524 } \ 525 else if (ISA_MIPS3) \ 526 { \ 527 builtin_define ("__mips=3"); \ 528 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \ 529 } \ 530 else if (ISA_MIPS4) \ 531 { \ 532 builtin_define ("__mips=4"); \ 533 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \ 534 } \ 535 else if (mips_isa >= MIPS_ISA_MIPS32 \ 536 && mips_isa < MIPS_ISA_MIPS64) \ 537 { \ 538 builtin_define ("__mips=32"); \ 539 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \ 540 } \ 541 else if (mips_isa >= MIPS_ISA_MIPS64) \ 542 { \ 543 builtin_define ("__mips=64"); \ 544 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ 545 } \ 546 if (mips_isa_rev > 0) \ 547 builtin_define_with_int_value ("__mips_isa_rev", \ 548 mips_isa_rev); \ 549 \ 550 switch (mips_abi) \ 551 { \ 552 case ABI_32: \ 553 builtin_define ("_ABIO32=1"); \ 554 builtin_define ("_MIPS_SIM=_ABIO32"); \ 555 break; \ 556 \ 557 case ABI_N32: \ 558 builtin_define ("_ABIN32=2"); \ 559 builtin_define ("_MIPS_SIM=_ABIN32"); \ 560 break; \ 561 \ 562 case ABI_64: \ 563 builtin_define ("_ABI64=3"); \ 564 builtin_define ("_MIPS_SIM=_ABI64"); \ 565 break; \ 566 \ 567 case ABI_O64: \ 568 builtin_define ("_ABIO64=4"); \ 569 builtin_define ("_MIPS_SIM=_ABIO64"); \ 570 break; \ 571 } \ 572 \ 573 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \ 574 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \ 575 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \ 576 builtin_define_with_int_value ("_MIPS_FPSET", \ 577 32 / MAX_FPRS_PER_FMT); \ 578 builtin_define_with_int_value ("_MIPS_SPFPSET", \ 579 TARGET_ODD_SPREG ? 32 : 16); \ 580 \ 581 /* These defines reflect the ABI in use, not whether the \ 582 FPU is directly accessible. */ \ 583 if (TARGET_NO_FLOAT) \ 584 builtin_define ("__mips_no_float"); \ 585 else if (TARGET_HARD_FLOAT_ABI) \ 586 builtin_define ("__mips_hard_float"); \ 587 else \ 588 builtin_define ("__mips_soft_float"); \ 589 \ 590 if (TARGET_SINGLE_FLOAT) \ 591 builtin_define ("__mips_single_float"); \ 592 \ 593 if (TARGET_PAIRED_SINGLE_FLOAT) \ 594 builtin_define ("__mips_paired_single_float"); \ 595 \ 596 if (mips_abs == MIPS_IEEE_754_2008) \ 597 builtin_define ("__mips_abs2008"); \ 598 \ 599 if (mips_nan == MIPS_IEEE_754_2008) \ 600 builtin_define ("__mips_nan2008"); \ 601 \ 602 if (TARGET_BIG_ENDIAN) \ 603 { \ 604 builtin_define_std ("MIPSEB"); \ 605 builtin_define ("_MIPSEB"); \ 606 } \ 607 else \ 608 { \ 609 builtin_define_std ("MIPSEL"); \ 610 builtin_define ("_MIPSEL"); \ 611 } \ 612 \ 613 /* Whether calls should go through $25. The separate __PIC__ \ 614 macro indicates whether abicalls code might use a GOT. */ \ 615 if (TARGET_ABICALLS) \ 616 builtin_define ("__mips_abicalls"); \ 617 \ 618 /* Whether Loongson vector modes are enabled. */ \ 619 if (TARGET_LOONGSON_MMI) \ 620 { \ 621 builtin_define ("__mips_loongson_vector_rev"); \ 622 builtin_define ("__mips_loongson_mmi"); \ 623 } \ 624 \ 625 /* Whether Loongson EXT modes are enabled. */ \ 626 if (TARGET_LOONGSON_EXT) \ 627 { \ 628 builtin_define ("__mips_loongson_ext"); \ 629 if (TARGET_LOONGSON_EXT2) \ 630 { \ 631 builtin_define ("__mips_loongson_ext2"); \ 632 builtin_define ("__mips_loongson_ext_rev=2"); \ 633 } \ 634 else \ 635 builtin_define ("__mips_loongson_ext_rev=1"); \ 636 } \ 637 \ 638 /* Historical Octeon macro. */ \ 639 if (TARGET_OCTEON) \ 640 builtin_define ("__OCTEON__"); \ 641 \ 642 if (TARGET_SYNCI) \ 643 builtin_define ("__mips_synci"); \ 644 \ 645 /* Macros dependent on the C dialect. */ \ 646 if (preprocessing_asm_p ()) \ 647 { \ 648 builtin_define_std ("LANGUAGE_ASSEMBLY"); \ 649 builtin_define ("_LANGUAGE_ASSEMBLY"); \ 650 } \ 651 else if (c_dialect_cxx ()) \ 652 { \ 653 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \ 654 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \ 655 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \ 656 } \ 657 else \ 658 { \ 659 builtin_define_std ("LANGUAGE_C"); \ 660 builtin_define ("_LANGUAGE_C"); \ 661 } \ 662 if (c_dialect_objc ()) \ 663 { \ 664 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \ 665 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \ 666 /* Bizarre, but retained for backwards compatibility. */ \ 667 builtin_define_std ("LANGUAGE_C"); \ 668 builtin_define ("_LANGUAGE_C"); \ 669 } \ 670 \ 671 if (mips_abi == ABI_EABI) \ 672 builtin_define ("__mips_eabi"); \ 673 \ 674 if (TARGET_CACHE_BUILTIN) \ 675 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \ 676 if (!ISA_HAS_LXC1_SXC1) \ 677 builtin_define ("__mips_no_lxc1_sxc1"); \ 678 if (!ISA_HAS_UNFUSED_MADD4 && !ISA_HAS_FUSED_MADD4) \ 679 builtin_define ("__mips_no_madd4"); \ 680 } \ 681 while (0) 682 683 /* Default target_flags if no switches are specified */ 684 685 #ifndef TARGET_DEFAULT 686 #define TARGET_DEFAULT 0 687 #endif 688 689 #ifndef TARGET_CPU_DEFAULT 690 #define TARGET_CPU_DEFAULT 0 691 #endif 692 693 #ifndef TARGET_ENDIAN_DEFAULT 694 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN 695 #endif 696 697 #ifdef IN_LIBGCC2 698 #undef TARGET_64BIT 699 /* Make this compile time constant for libgcc2 */ 700 #ifdef __mips64 701 #define TARGET_64BIT 1 702 #else 703 #define TARGET_64BIT 0 704 #endif 705 #endif /* IN_LIBGCC2 */ 706 707 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code 708 when compiled with hardware floating point. This is because MIPS16 709 code cannot save and restore the floating-point registers, which is 710 important if in a mixed MIPS16/non-MIPS16 environment. */ 711 712 #ifdef IN_LIBGCC2 713 #if __mips_hard_float 714 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__)) 715 #endif 716 #endif /* IN_LIBGCC2 */ 717 718 #define TARGET_LIBGCC_SDATA_SECTION ".sdata" 719 720 #ifndef MULTILIB_ENDIAN_DEFAULT 721 #if TARGET_ENDIAN_DEFAULT == 0 722 #define MULTILIB_ENDIAN_DEFAULT "EL" 723 #else 724 #define MULTILIB_ENDIAN_DEFAULT "EB" 725 #endif 726 #endif 727 728 #ifndef MULTILIB_ISA_DEFAULT 729 #if MIPS_ISA_DEFAULT == MIPS_ISA_MIPS1 730 #define MULTILIB_ISA_DEFAULT "mips1" 731 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS2 732 #define MULTILIB_ISA_DEFAULT "mips2" 733 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS3 734 #define MULTILIB_ISA_DEFAULT "mips3" 735 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS4 736 #define MULTILIB_ISA_DEFAULT "mips4" 737 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS32 738 #define MULTILIB_ISA_DEFAULT "mips32" 739 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS32R2 740 #define MULTILIB_ISA_DEFAULT "mips32r2" 741 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS32R6 742 #define MULTILIB_ISA_DEFAULT "mips32r6" 743 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS64 744 #define MULTILIB_ISA_DEFAULT "mips64" 745 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS64R2 746 #define MULTILIB_ISA_DEFAULT "mips64r2" 747 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS64R6 748 #define MULTILIB_ISA_DEFAULT "mips64r6" 749 #else 750 #define MULTILIB_ISA_DEFAULT "mips1" 751 #endif 752 #endif 753 754 #ifndef MIPS_ABI_DEFAULT 755 #define MIPS_ABI_DEFAULT ABI_32 756 #endif 757 758 /* Use the most portable ABI flag for the ASM specs. */ 759 760 #if MIPS_ABI_DEFAULT == ABI_32 761 #define MULTILIB_ABI_DEFAULT "mabi=32" 762 #elif MIPS_ABI_DEFAULT == ABI_O64 763 #define MULTILIB_ABI_DEFAULT "mabi=o64" 764 #elif MIPS_ABI_DEFAULT == ABI_N32 765 #define MULTILIB_ABI_DEFAULT "mabi=n32" 766 #elif MIPS_ABI_DEFAULT == ABI_64 767 #define MULTILIB_ABI_DEFAULT "mabi=64" 768 #elif MIPS_ABI_DEFAULT == ABI_EABI 769 #define MULTILIB_ABI_DEFAULT "mabi=eabi" 770 #endif 771 772 #ifndef MULTILIB_DEFAULTS 773 #define MULTILIB_DEFAULTS \ 774 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT } 775 #endif 776 777 /* We must pass -EL to the linker by default for little endian embedded 778 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the 779 linker will default to using big-endian output files. The OUTPUT_FORMAT 780 line must be in the linker script, otherwise -EB/-EL will not work. */ 781 782 #ifndef ENDIAN_SPEC 783 #if TARGET_ENDIAN_DEFAULT == 0 784 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}" 785 #else 786 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}" 787 #endif 788 #endif 789 790 /* A spec condition that matches all non-mips16 -mips arguments. */ 791 792 #define MIPS_ISA_LEVEL_OPTION_SPEC \ 793 "mips1|mips2|mips3|mips4|mips32*|mips64*" 794 795 /* A spec condition that matches all non-mips16 architecture arguments. */ 796 797 #define MIPS_ARCH_OPTION_SPEC \ 798 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*" 799 800 /* A spec that infers a -mips argument from an -march argument. */ 801 802 #define MIPS_ISA_LEVEL_SPEC \ 803 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \ 804 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \ 805 %{march=mips2|march=r6000:-mips2} \ 806 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \ 807 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \ 808 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \ 809 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \ 810 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \ 811 |march=34k*|march=74k*|march=m14k*|march=1004k* \ 812 |march=interaptiv: -mips32r2} \ 813 %{march=mips32r3: -mips32r3} \ 814 %{march=mips32r5|march=p5600|march=m5100|march=m5101: -mips32r5} \ 815 %{march=mips32r6: -mips32r6} \ 816 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ 817 |march=xlr: -mips64} \ 818 %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=gs264e \ 819 |march=octeon|march=xlp: -mips64r2} \ 820 %{march=mips64r3: -mips64r3} \ 821 %{march=mips64r5: -mips64r5} \ 822 %{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}" 823 824 /* A spec that injects the default multilib ISA if no architecture is 825 specified. */ 826 827 #define MIPS_DEFAULT_ISA_LEVEL_SPEC \ 828 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \ 829 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}" 830 831 /* A spec that infers a -mhard-float or -msoft-float setting from an 832 -march argument. Note that soft-float and hard-float code are not 833 link-compatible. */ 834 835 #define MIPS_ARCH_FLOAT_SPEC \ 836 "%{mhard-float|msoft-float|mno-float|march=mips*:; \ 837 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \ 838 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \ 839 |march=m14k*|march=m5101|march=octeon|march=xlr: -msoft-float; \ 840 march=*: -mhard-float}" 841 842 /* A spec condition that matches 32-bit options. It only works if 843 MIPS_ISA_LEVEL_SPEC has been applied. */ 844 845 #define MIPS_32BIT_OPTION_SPEC \ 846 "mips1|mips2|mips32*|mgp32" 847 848 /* A spec condition that matches architectures should be targeted with 849 o32 FPXX for compatibility reasons. */ 850 #define MIPS_FPXX_OPTION_SPEC \ 851 "mips2|mips3|mips4|mips5|mips32|mips32r2|mips32r3|mips32r5| \ 852 mips64|mips64r2|mips64r3|mips64r5" 853 854 /* Infer a -msynci setting from a -mips argument, on the assumption that 855 -msynci is desired where possible. */ 856 #define MIPS_ISA_SYNCI_SPEC \ 857 "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips32r6|mips64r2 \ 858 |mips64r3|mips64r5|mips64r6:-msynci;:-mno-synci}}" 859 860 /* Infer a -mnan=2008 setting from a -mips argument. */ 861 #define MIPS_ISA_NAN2008_SPEC \ 862 "%{mnan*:;mips32r6|mips64r6:-mnan=2008;march=m51*: \ 863 %{!msoft-float:-mnan=2008}}" 864 865 #if (MIPS_ABI_DEFAULT == ABI_O64 \ 866 || MIPS_ABI_DEFAULT == ABI_N32 \ 867 || MIPS_ABI_DEFAULT == ABI_64) 868 #define OPT_ARCH64 "mabi=32|mgp32:;" 869 #define OPT_ARCH32 "mabi=32|mgp32" 870 #else 871 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64" 872 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;" 873 #endif 874 875 /* Support for a compile-time default CPU, et cetera. The rules are: 876 --with-arch is ignored if -march is specified or a -mips is specified 877 (other than -mips16); likewise --with-arch-32 and --with-arch-64. 878 --with-tune is ignored if -mtune is specified; likewise 879 --with-tune-32 and --with-tune-64. 880 --with-abi is ignored if -mabi is specified. 881 --with-float is ignored if -mhard-float or -msoft-float are 882 specified. 883 --with-fpu is ignored if -msoft-float, -msingle-float or -mdouble-float are 884 specified. 885 --with-nan is ignored if -mnan is specified. 886 --with-fp-32 is ignored if -msoft-float, -msingle-float, -mmsa or -mfp are 887 specified. 888 --with-odd-spreg-32 is ignored if -msoft-float, -msingle-float, -modd-spreg 889 or -mno-odd-spreg are specified. 890 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are 891 specified. */ 892 #define OPTION_DEFAULT_SPECS \ 893 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \ 894 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \ 895 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \ 896 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 897 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \ 898 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \ 899 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \ 900 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \ 901 {"fpu", "%{!msoft-float:%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}}" }, \ 902 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \ 903 {"fp_32", "%{" OPT_ARCH32 \ 904 ":%{!msoft-float:%{!msingle-float:%{!mfp*:%{!mmsa:-mfp%(VALUE)}}}}}" }, \ 905 {"odd_spreg_32", "%{" OPT_ARCH32 ":%{!msoft-float:%{!msingle-float:" \ 906 "%{!modd-spreg:%{!mno-odd-spreg:-m%(VALUE)}}}}}" }, \ 907 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \ 908 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \ 909 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \ 910 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }, \ 911 {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" }, \ 912 {"madd4", "%{!mmadd4:%{!mno-madd4:-m%(VALUE)}}" } \ 913 914 /* A spec that infers the: 915 -mnan=2008 setting from a -mips argument, 916 -mdsp setting from a -march argument. 917 -mloongson-mmi setting from a -march argument. */ 918 #define BASE_DRIVER_SELF_SPECS \ 919 MIPS_ISA_NAN2008_SPEC, \ 920 MIPS_ASE_DSP_SPEC, \ 921 MIPS_ASE_LOONGSON_MMI_SPEC, \ 922 MIPS_ASE_LOONGSON_EXT_SPEC, \ 923 MIPS_ASE_MSA_SPEC 924 925 926 #define MIPS_ASE_DSP_SPEC \ 927 "%{!mno-dsp: \ 928 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k* \ 929 |march=interaptiv: -mdsp} \ 930 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}" 931 932 #define MIPS_ASE_LOONGSON_MMI_SPEC \ 933 "%{!mno-loongson-mmi: \ 934 %{march=loongson2e|march=loongson2f|march=loongson3a: -mloongson-mmi}}" 935 936 #define MIPS_ASE_LOONGSON_EXT_SPEC \ 937 "%{!mno-loongson-ext: \ 938 %{march=loongson3a|march=gs464: -mloongson-ext} \ 939 %{march=gs464e|march=gs264e: %{!mno-loongson-ext2: \ 940 -mloongson-ext2 -mloongson-ext}}}" 941 942 #define MIPS_ASE_MSA_SPEC \ 943 "%{!mno-msa: \ 944 %{march=gs264e: -mmsa}}" 945 946 #define DRIVER_SELF_SPECS \ 947 MIPS_ISA_LEVEL_SPEC, \ 948 BASE_DRIVER_SELF_SPECS 949 950 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \ 951 && ISA_HAS_COND_TRAP) 952 953 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16) 954 955 /* True if the ABI can only work with 64-bit integer registers. We 956 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but 957 otherwise floating-point registers must also be 64-bit. */ 958 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64) 959 960 /* Likewise for 32-bit regs. */ 961 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32) 962 963 /* True if the file format uses 64-bit symbols. At present, this is 964 only true for n64, which uses 64-bit ELF. */ 965 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64) 966 967 /* True if symbols are 64 bits wide. This is usually determined by 968 the ABI's file format, but it can be overridden by -msym32. Note that 969 overriding the size with -msym32 changes the ABI of relocatable objects, 970 although it doesn't change the ABI of a fully-linked object. */ 971 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \ 972 && Pmode == DImode \ 973 && !TARGET_SYM32) 974 975 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */ 976 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \ 977 || ISA_MIPS4 \ 978 || ISA_MIPS64 \ 979 || ISA_MIPS64R2 \ 980 || ISA_MIPS64R3 \ 981 || ISA_MIPS64R5 \ 982 || ISA_MIPS64R6) 983 984 #define ISA_HAS_JR (mips_isa_rev <= 5) 985 986 #define ISA_HAS_DELAY_SLOTS 1 987 988 #define ISA_HAS_COMPACT_BRANCHES (mips_isa_rev >= 6) 989 990 /* ISA has branch likely instructions (e.g. mips2). */ 991 /* Disable branchlikely for tx39 until compare rewrite. They haven't 992 been generated up to this point. */ 993 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 && mips_isa_rev <= 5) 994 995 /* ISA has 32 single-precision registers. */ 996 #define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \ 997 && !TARGET_GS464) \ 998 || TARGET_FLOAT64 \ 999 || TARGET_MIPS5900) 1000 1001 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */ 1002 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \ 1003 || TARGET_MIPS5400 \ 1004 || TARGET_MIPS5500 \ 1005 || TARGET_MIPS5900 \ 1006 || TARGET_MIPS7000 \ 1007 || TARGET_MIPS9000 \ 1008 || TARGET_MAD \ 1009 || (mips_isa_rev >= 1 \ 1010 && mips_isa_rev <= 5)) \ 1011 && !TARGET_MIPS16) 1012 1013 /* ISA has a three-operand multiplication instruction. */ 1014 #define ISA_HAS_DMUL3 (TARGET_64BIT \ 1015 && TARGET_OCTEON \ 1016 && !TARGET_MIPS16) 1017 1018 /* ISA has HI and LO registers. */ 1019 #define ISA_HAS_HILO (mips_isa_rev <= 5) 1020 1021 /* ISA supports instructions DMULT and DMULTU. */ 1022 #define ISA_HAS_DMULT (TARGET_64BIT \ 1023 && !TARGET_MIPS5900 \ 1024 && mips_isa_rev <= 5) 1025 1026 /* ISA supports instructions MULT and MULTU. */ 1027 #define ISA_HAS_MULT (mips_isa_rev <= 5) 1028 1029 /* ISA supports instructions MUL, MULU, MUH, MUHU. */ 1030 #define ISA_HAS_R6MUL (mips_isa_rev >= 6) 1031 1032 /* ISA supports instructions DMUL, DMULU, DMUH, DMUHU. */ 1033 #define ISA_HAS_R6DMUL (TARGET_64BIT && mips_isa_rev >= 6) 1034 1035 /* For Loongson, it is preferable to use the Loongson-specific division and 1036 modulo instructions instead of the regular (D)DIV(U) instruction, 1037 because the former are faster and can also have the effect of reducing 1038 code size. */ 1039 #define ISA_AVOID_DIV_HILO ((TARGET_LOONGSON_2EF \ 1040 || TARGET_GS464) \ 1041 && !TARGET_MIPS16) 1042 1043 /* ISA supports instructions DDIV and DDIVU. */ 1044 #define ISA_HAS_DDIV (TARGET_64BIT \ 1045 && !TARGET_MIPS5900 \ 1046 && !ISA_AVOID_DIV_HILO \ 1047 && mips_isa_rev <= 5) 1048 1049 /* ISA supports instructions DIV and DIVU. 1050 This is always true, but the macro is needed for ISA_HAS_<D>DIV 1051 in mips.md. */ 1052 #define ISA_HAS_DIV (!ISA_AVOID_DIV_HILO \ 1053 && mips_isa_rev <= 5) 1054 1055 /* ISA supports instructions DIV, DIVU, MOD and MODU. */ 1056 #define ISA_HAS_R6DIV (mips_isa_rev >= 6) 1057 1058 /* ISA supports instructions DDIV, DDIVU, DMOD and DMODU. */ 1059 #define ISA_HAS_R6DDIV (TARGET_64BIT && mips_isa_rev >= 6) 1060 1061 /* ISA has the floating-point conditional move instructions introduced 1062 in mips4. */ 1063 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \ 1064 || (mips_isa_rev >= 1 \ 1065 && mips_isa_rev <= 5)) \ 1066 && !TARGET_MIPS5500 \ 1067 && !TARGET_MIPS16) 1068 1069 /* ISA has the integer conditional move instructions introduced in mips4 and 1070 ST Loongson 2E/2F. */ 1071 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \ 1072 || TARGET_MIPS5900 \ 1073 || TARGET_LOONGSON_2EF) 1074 1075 /* ISA has LDC1 and SDC1. */ 1076 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \ 1077 && !TARGET_MIPS5900 \ 1078 && !TARGET_MIPS16) 1079 1080 /* ISA has the mips4 FP condition code instructions: FP-compare to CC, 1081 branch on CC, and move (both FP and non-FP) on CC. */ 1082 #define ISA_HAS_8CC (ISA_MIPS4 \ 1083 || (mips_isa_rev >= 1 \ 1084 && mips_isa_rev <= 5)) 1085 1086 /* ISA has the FP condition code instructions that store the flag in an 1087 FP register. */ 1088 #define ISA_HAS_CCF (mips_isa_rev >= 6) 1089 1090 #define ISA_HAS_SEL (mips_isa_rev >= 6) 1091 1092 /* This is a catch all for other mips4 instructions: indexed load, the 1093 FP madd and msub instructions, and the FP recip and recip sqrt 1094 instructions. Note that this macro should only be used by other 1095 ISA_HAS_* macros. */ 1096 #define ISA_HAS_FP4 ((ISA_MIPS4 \ 1097 || ISA_MIPS64 \ 1098 || (mips_isa_rev >= 2 \ 1099 && mips_isa_rev <= 5)) \ 1100 && !TARGET_MIPS16) 1101 1102 /* ISA has floating-point indexed load and store instructions 1103 (LWXC1, LDXC1, SWXC1 and SDXC1). */ 1104 #define ISA_HAS_LXC1_SXC1 (ISA_HAS_FP4 \ 1105 && mips_lxc1_sxc1) 1106 1107 /* ISA has paired-single instructions. */ 1108 #define ISA_HAS_PAIRED_SINGLE ((ISA_MIPS64 \ 1109 || (mips_isa_rev >= 2 \ 1110 && mips_isa_rev <= 5)) \ 1111 && !TARGET_OCTEON) 1112 1113 /* ISA has conditional trap instructions. */ 1114 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \ 1115 && !TARGET_MIPS16) 1116 1117 /* ISA has conditional trap with immediate instructions. */ 1118 #define ISA_HAS_COND_TRAPI (!ISA_MIPS1 \ 1119 && mips_isa_rev <= 5 \ 1120 && !TARGET_MIPS16) 1121 1122 /* ISA has integer multiply-accumulate instructions, madd and msub. */ 1123 #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1 \ 1124 && mips_isa_rev <= 5) 1125 1126 /* Integer multiply-accumulate instructions should be generated. */ 1127 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16) 1128 1129 /* ISA has 4 operand fused madd instructions of the form 1130 'd = [+-] (a * b [+-] c)'. */ 1131 #define ISA_HAS_FUSED_MADD4 (mips_madd4 \ 1132 && (TARGET_MIPS8000 \ 1133 || TARGET_GS464 \ 1134 || TARGET_GS464E \ 1135 || TARGET_GS264E)) 1136 1137 /* ISA has 4 operand unfused madd instructions of the form 1138 'd = [+-] (a * b [+-] c)'. */ 1139 #define ISA_HAS_UNFUSED_MADD4 (mips_madd4 \ 1140 && ISA_HAS_FP4 \ 1141 && !TARGET_MIPS8000 \ 1142 && !TARGET_GS464 \ 1143 && !TARGET_GS464E \ 1144 && !TARGET_GS264E) 1145 1146 /* ISA has 3 operand r6 fused madd instructions of the form 1147 'c = c [+-] (a * b)'. */ 1148 #define ISA_HAS_FUSED_MADDF (mips_isa_rev >= 6) 1149 1150 /* ISA has 3 operand loongson fused madd instructions of the form 1151 'c = [+-] (a * b [+-] c)'. */ 1152 #define ISA_HAS_FUSED_MADD3 TARGET_LOONGSON_2EF 1153 1154 /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The 1155 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when 1156 doubles are stored in pairs of FPRs, so for safety's sake, we apply 1157 this restriction to the MIPS IV ISA too. */ 1158 #define ISA_HAS_FP_RECIP_RSQRT(MODE) \ 1159 (((ISA_HAS_FP4 \ 1160 && ((MODE) == SFmode \ 1161 || ((TARGET_FLOAT64 \ 1162 || mips_isa_rev >= 2) \ 1163 && (MODE) == DFmode))) \ 1164 || (((MODE) == SFmode \ 1165 || (MODE) == DFmode) \ 1166 && (mips_isa_rev >= 6)) \ 1167 || (TARGET_SB1 \ 1168 && (MODE) == V2SFmode)) \ 1169 && !TARGET_MIPS16) 1170 1171 #define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 && !TARGET_MIPS16) 1172 1173 #define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5) 1174 1175 #define ISA_HAS_IEEE_754_2008 (mips_isa_rev >= 2) 1176 1177 /* ISA has count leading zeroes/ones instruction (not implemented). */ 1178 #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16) 1179 1180 /* ISA has count trailing zeroes/ones instruction. */ 1181 #define ISA_HAS_CTZ_CTO (TARGET_LOONGSON_EXT2) 1182 1183 /* ISA has three operand multiply instructions that put 1184 the high part in an accumulator: mulhi or mulhiu. */ 1185 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \ 1186 || TARGET_MIPS5500 \ 1187 || TARGET_SR71K) \ 1188 && !TARGET_MIPS16) 1189 1190 /* ISA has three operand multiply instructions that negate the 1191 result and put the result in an accumulator. */ 1192 #define ISA_HAS_MULS ((TARGET_MIPS5400 \ 1193 || TARGET_MIPS5500 \ 1194 || TARGET_SR71K) \ 1195 && !TARGET_MIPS16) 1196 1197 /* ISA has three operand multiply instructions that subtract the 1198 result from a 4th operand and put the result in an accumulator. */ 1199 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \ 1200 || TARGET_MIPS5500 \ 1201 || TARGET_SR71K) \ 1202 && !TARGET_MIPS16) 1203 1204 /* ISA has three operand multiply instructions that add the result 1205 to a 4th operand and put the result in an accumulator. */ 1206 #define ISA_HAS_MACC ((TARGET_MIPS4120 \ 1207 || TARGET_MIPS4130 \ 1208 || TARGET_MIPS5400 \ 1209 || TARGET_MIPS5500 \ 1210 || TARGET_SR71K) \ 1211 && !TARGET_MIPS16) 1212 1213 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */ 1214 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \ 1215 || TARGET_MIPS4130) \ 1216 && !TARGET_MIPS16) 1217 1218 /* ISA has the "ror" (rotate right) instructions. */ 1219 #define ISA_HAS_ROR ((mips_isa_rev >= 2 \ 1220 || TARGET_MIPS5400 \ 1221 || TARGET_MIPS5500 \ 1222 || TARGET_SR71K \ 1223 || TARGET_SMARTMIPS) \ 1224 && !TARGET_MIPS16) 1225 1226 /* ISA has the WSBH (word swap bytes within halfwords) instruction. 1227 64-bit targets also provide DSBH and DSHD. */ 1228 #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16) 1229 1230 /* ISA has data prefetch instructions. This controls use of 'pref'. */ 1231 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \ 1232 || TARGET_LOONGSON_2EF \ 1233 || TARGET_MIPS5900 \ 1234 || mips_isa_rev >= 1) \ 1235 && !TARGET_MIPS16) 1236 1237 /* ISA has data prefetch, LL and SC with limited 9-bit displacement. */ 1238 #define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6) 1239 1240 /* ISA has data indexed prefetch instructions. This controls use of 1241 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. 1242 (prefx is a cop1x instruction, so can only be used if FP is 1243 enabled.) */ 1244 #define ISA_HAS_PREFETCHX (ISA_HAS_FP4 \ 1245 || TARGET_LOONGSON_EXT \ 1246 || TARGET_LOONGSON_EXT2) 1247 1248 /* True if trunc.w.s and trunc.w.d are real (not synthetic) 1249 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d 1250 also requires TARGET_DOUBLE_FLOAT. */ 1251 #define ISA_HAS_TRUNC_W (!ISA_MIPS1) 1252 1253 /* ISA includes the MIPS32r2 seb and seh instructions. */ 1254 #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16) 1255 1256 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */ 1257 #define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16) 1258 1259 /* ISA has instructions for accessing top part of 64-bit fp regs. */ 1260 #define ISA_HAS_MXHC1 (!TARGET_FLOAT32 \ 1261 && mips_isa_rev >= 2) 1262 1263 /* ISA has lwxs instruction (load w/scaled index address. */ 1264 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \ 1265 && !TARGET_MIPS16) 1266 1267 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */ 1268 #define ISA_HAS_LBX (TARGET_OCTEON2) 1269 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2) 1270 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2) 1271 #define ISA_HAS_LHUX (TARGET_OCTEON2) 1272 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2) 1273 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT) 1274 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \ 1275 && TARGET_64BIT) 1276 1277 /* The DSP ASE is available. */ 1278 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16) 1279 1280 /* Revision 2 of the DSP ASE is available. */ 1281 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16) 1282 1283 /* The MSA ASE is available. */ 1284 #define ISA_HAS_MSA (TARGET_MSA && !TARGET_MIPS16) 1285 1286 /* True if the result of a load is not available to the next instruction. 1287 A nop will then be needed between instructions like "lw $4,..." 1288 and "addiu $4,$4,1". */ 1289 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \ 1290 && !TARGET_MIPS3900 \ 1291 && !TARGET_MIPS5900 \ 1292 && !TARGET_MIPS16 \ 1293 && !TARGET_MICROMIPS) 1294 1295 /* Likewise mtc1 and mfc1. */ 1296 #define ISA_HAS_XFER_DELAY (mips_isa <= MIPS_ISA_MIPS3 \ 1297 && !TARGET_MIPS5900 \ 1298 && !TARGET_LOONGSON_2EF) 1299 1300 /* Likewise floating-point comparisons. */ 1301 #define ISA_HAS_FCMP_DELAY (mips_isa <= MIPS_ISA_MIPS3 \ 1302 && !TARGET_MIPS5900 \ 1303 && !TARGET_LOONGSON_2EF) 1304 1305 /* True if mflo and mfhi can be immediately followed by instructions 1306 which write to the HI and LO registers. 1307 1308 According to MIPS specifications, MIPS ISAs I, II, and III need 1309 (at least) two instructions between the reads of HI/LO and 1310 instructions which write them, and later ISAs do not. Contradicting 1311 the MIPS specifications, some MIPS IV processor user manuals (e.g. 1312 the UM for the NEC Vr5000) document needing the instructions between 1313 HI/LO reads and writes, as well. Therefore, we declare only MIPS32, 1314 MIPS64 and later ISAs to have the interlocks, plus any specific 1315 earlier-ISA CPUs for which CPU documentation declares that the 1316 instructions are really interlocked. */ 1317 #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \ 1318 || TARGET_MIPS5500 \ 1319 || TARGET_MIPS5900 \ 1320 || TARGET_LOONGSON_2EF) 1321 1322 /* ISA includes synci, jr.hb and jalr.hb. */ 1323 #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16) 1324 1325 /* ISA includes sync. */ 1326 #define ISA_HAS_SYNC ((mips_isa >= MIPS_ISA_MIPS2 || TARGET_MIPS3900) && !TARGET_MIPS16) 1327 #define GENERATE_SYNC \ 1328 (target_flags_explicit & MASK_LLSC \ 1329 ? TARGET_LLSC && !TARGET_MIPS16 \ 1330 : ISA_HAS_SYNC) 1331 1332 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC 1333 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC 1334 instructions. */ 1335 #define ISA_HAS_LL_SC (mips_isa >= MIPS_ISA_MIPS2 && !TARGET_MIPS5900 && !TARGET_MIPS16) 1336 #define GENERATE_LL_SC \ 1337 (target_flags_explicit & MASK_LLSC \ 1338 ? TARGET_LLSC && !TARGET_MIPS16 \ 1339 : ISA_HAS_LL_SC) 1340 1341 #define ISA_HAS_SWAP (TARGET_XLP) 1342 #define ISA_HAS_LDADD (TARGET_XLP) 1343 1344 /* ISA includes the baddu instruction. */ 1345 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16) 1346 1347 /* ISA includes the bbit* instructions. */ 1348 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16) 1349 1350 /* ISA includes the cins instruction. */ 1351 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16) 1352 1353 /* ISA includes the exts instruction. */ 1354 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16) 1355 1356 /* ISA includes the seq and sne instructions. */ 1357 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16) 1358 1359 /* ISA includes the pop instruction. */ 1360 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16) 1361 1362 /* The CACHE instruction is available in non-MIPS16 code. */ 1363 #define TARGET_CACHE_BUILTIN (mips_isa >= MIPS_ISA_MIPS3) 1364 1365 /* The CACHE instruction is available. */ 1366 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16) 1367 1368 /* Tell collect what flags to pass to nm. */ 1369 #ifndef NM_FLAGS 1370 #define NM_FLAGS "-Bn" 1371 #endif 1372 1373 1374 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to 1375 the assembler. It may be overridden by subtargets. 1376 1377 Beginning with gas 2.13, -mdebug must be passed to correctly handle 1378 COFF debugging info. */ 1379 1380 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC 1381 #define SUBTARGET_ASM_DEBUGGING_SPEC "\ 1382 %{g} %{g0} %{g1} %{g2} %{g3} \ 1383 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \ 1384 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \ 1385 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3}" 1386 #endif 1387 1388 /* FP_ASM_SPEC represents the floating-point options that must be passed 1389 to the assembler when FPXX support exists. Prior to that point the 1390 assembler could accept the options but were not required for 1391 correctness. We only add the options when absolutely necessary 1392 because passing -msoft-float to the assembler will cause it to reject 1393 all hard-float instructions which may require some user code to be 1394 updated. */ 1395 1396 #ifdef HAVE_AS_DOT_MODULE 1397 #define FP_ASM_SPEC "\ 1398 %{mhard-float} %{msoft-float} \ 1399 %{msingle-float} %{mdouble-float}" 1400 #else 1401 #define FP_ASM_SPEC 1402 #endif 1403 1404 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be 1405 overridden by subtargets. */ 1406 1407 #ifndef SUBTARGET_ASM_SPEC 1408 #define SUBTARGET_ASM_SPEC "" 1409 #endif 1410 1411 #undef ASM_SPEC 1412 #define ASM_SPEC "\ 1413 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \ 1414 %{mips32*} %{mips64*} \ 1415 %{mips16} %{mno-mips16:-no-mips16} \ 1416 %{mmicromips} %{mno-micromips} \ 1417 %{mips3d} %{mno-mips3d:-no-mips3d} \ 1418 %{mdmx} %{mno-mdmx:-no-mdmx} \ 1419 %{mdsp} %{mno-dsp} \ 1420 %{mdspr2} %{mno-dspr2} \ 1421 %{mmcu} %{mno-mcu} \ 1422 %{meva} %{mno-eva} \ 1423 %{mvirt} %{mno-virt} \ 1424 %{mxpa} %{mno-xpa} \ 1425 %{mcrc} %{mno-crc} \ 1426 %{mginv} %{mno-ginv} \ 1427 %{mmsa} %{mno-msa} \ 1428 %{mloongson-mmi} %{mno-loongson-mmi} \ 1429 %{mloongson-ext} %{mno-loongson-ext} \ 1430 %{mloongson-ext2} %{mno-loongson-ext2} \ 1431 %{msmartmips} %{mno-smartmips} \ 1432 %{mmt} %{mno-mt} \ 1433 %{mfix-r5900} %{mno-fix-r5900} \ 1434 %{mfix-rm7000} %{mno-fix-rm7000} \ 1435 %{mfix-vr4120} %{mfix-vr4130} \ 1436 %{mfix-24k} \ 1437 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \ 1438 %(subtarget_asm_debugging_spec) \ 1439 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \ 1440 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \ 1441 %{mfp32} %{mfpxx} %{mfp64} %{mnan=*} \ 1442 %{modd-spreg} %{mno-odd-spreg} \ 1443 %{mshared} %{mno-shared} \ 1444 %{msym32} %{mno-sym32} \ 1445 %{mtune=*}" \ 1446 FP_ASM_SPEC "\ 1447 %(subtarget_asm_spec)" 1448 1449 /* Extra switches sometimes passed to the linker. */ 1450 1451 #ifndef LINK_SPEC 1452 #define LINK_SPEC "\ 1453 %(endian_spec) \ 1454 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \ 1455 %{shared}" 1456 #endif /* LINK_SPEC defined */ 1457 1458 1459 /* Specs for the compiler proper */ 1460 1461 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be 1462 overridden by subtargets. */ 1463 #ifndef SUBTARGET_CC1_SPEC 1464 #define SUBTARGET_CC1_SPEC "" 1465 #endif 1466 1467 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */ 1468 1469 #undef CC1_SPEC 1470 #define CC1_SPEC "\ 1471 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \ 1472 %(subtarget_cc1_spec)" 1473 1474 /* Preprocessor specs. */ 1475 1476 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be 1477 overridden by subtargets. */ 1478 #ifndef SUBTARGET_CPP_SPEC 1479 #define SUBTARGET_CPP_SPEC "" 1480 #endif 1481 1482 #define CPP_SPEC "%(subtarget_cpp_spec)" 1483 1484 /* This macro defines names of additional specifications to put in the specs 1485 that can be used in various specifications like CC1_SPEC. Its definition 1486 is an initializer with a subgrouping for each command option. 1487 1488 Each subgrouping contains a string constant, that defines the 1489 specification name, and a string constant that used by the GCC driver 1490 program. 1491 1492 Do not define this macro if it does not need to do anything. */ 1493 1494 #define EXTRA_SPECS \ 1495 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \ 1496 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 1497 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \ 1498 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ 1499 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \ 1500 { "endian_spec", ENDIAN_SPEC }, \ 1501 SUBTARGET_EXTRA_SPECS 1502 1503 #ifndef SUBTARGET_EXTRA_SPECS 1504 #define SUBTARGET_EXTRA_SPECS 1505 #endif 1506 1507 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */ 1508 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */ 1509 1510 #ifndef PREFERRED_DEBUGGING_TYPE 1511 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 1512 #endif 1513 1514 /* The size of DWARF addresses should be the same as the size of symbols 1515 in the target file format. They shouldn't depend on things like -msym32, 1516 because many DWARF consumers do not allow the mixture of address sizes 1517 that one would then get from linking -msym32 code with -msym64 code. 1518 1519 Note that the default POINTER_SIZE test is not appropriate for MIPS. 1520 EABI64 has 64-bit pointers but uses 32-bit ELF. */ 1521 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4) 1522 1523 /* By default, turn on GDB extensions. */ 1524 #define DEFAULT_GDB_EXTENSIONS 1 1525 1526 /* Registers may have a prefix which can be ignored when matching 1527 user asm and register definitions. */ 1528 #ifndef REGISTER_PREFIX 1529 #define REGISTER_PREFIX "$" 1530 #endif 1531 1532 /* Local compiler-generated symbols must have a prefix that the assembler 1533 understands. By default, this is $, although some targets (e.g., 1534 NetBSD-ELF) need to override this. */ 1535 1536 #ifndef LOCAL_LABEL_PREFIX 1537 #define LOCAL_LABEL_PREFIX "$" 1538 #endif 1539 1540 /* By default on the mips, external symbols do not have an underscore 1541 prepended, but some targets (e.g., NetBSD) require this. */ 1542 1543 #ifndef USER_LABEL_PREFIX 1544 #define USER_LABEL_PREFIX "" 1545 #endif 1546 1547 /* On Sun 4, this limit is 2048. We use 1500 to be safe, 1548 since the length can run past this up to a continuation point. */ 1549 #undef DBX_CONTIN_LENGTH 1550 #define DBX_CONTIN_LENGTH 1500 1551 1552 /* How to renumber registers for dbx and gdb. */ 1553 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO] 1554 1555 /* The mapping from gcc register number to DWARF 2 CFA column number. */ 1556 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO] 1557 1558 /* The DWARF 2 CFA column which tracks the return address. */ 1559 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM 1560 1561 /* Before the prologue, RA lives in r31. */ 1562 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) 1563 1564 /* Describe how we implement __builtin_eh_return. */ 1565 #define EH_RETURN_DATA_REGNO(N) \ 1566 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM) 1567 1568 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3) 1569 1570 #define EH_USES(N) mips_eh_uses (N) 1571 1572 /* Offsets recorded in opcodes are a multiple of this alignment factor. 1573 The default for this in 64-bit mode is 8, which causes problems with 1574 SFmode register saves. */ 1575 #define DWARF_CIE_DATA_ALIGNMENT -4 1576 1577 /* Correct the offset of automatic variables and arguments. Note that 1578 the MIPS debug format wants all automatic variables and arguments 1579 to be in terms of the virtual frame pointer (stack pointer before 1580 any adjustment in the function), while the MIPS 3.0 linker wants 1581 the frame pointer to be the stack pointer after the initial 1582 adjustment. */ 1583 1584 #define DEBUGGER_AUTO_OFFSET(X) \ 1585 mips_debugger_offset (X, (HOST_WIDE_INT) 0) 1586 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \ 1587 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET) 1588 1589 /* Target machine storage layout */ 1590 1591 #define BITS_BIG_ENDIAN 0 1592 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 1593 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 1594 1595 #define MAX_BITS_PER_WORD 64 1596 1597 /* Width of a word, in units (bytes). */ 1598 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 1599 #ifndef IN_LIBGCC2 1600 #define MIN_UNITS_PER_WORD 4 1601 #endif 1602 1603 /* Width of a MSA vector register in bytes. */ 1604 #define UNITS_PER_MSA_REG 16 1605 /* Width of a MSA vector register in bits. */ 1606 #define BITS_PER_MSA_REG (UNITS_PER_MSA_REG * BITS_PER_UNIT) 1607 1608 /* For MIPS, width of a floating point register. */ 1609 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4) 1610 1611 /* The number of consecutive floating-point registers needed to store the 1612 largest format supported by the FPU. */ 1613 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2) 1614 1615 /* The number of consecutive floating-point registers needed to store the 1616 smallest format supported by the FPU. */ 1617 #define MIN_FPRS_PER_FMT \ 1618 (TARGET_ODD_SPREG ? 1 : MAX_FPRS_PER_FMT) 1619 1620 /* The largest size of value that can be held in floating-point 1621 registers and moved with a single instruction. */ 1622 #define UNITS_PER_HWFPVALUE \ 1623 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG) 1624 1625 /* The largest size of value that can be held in floating-point 1626 registers. */ 1627 #define UNITS_PER_FPVALUE \ 1628 (TARGET_SOFT_FLOAT_ABI ? 0 \ 1629 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \ 1630 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT) 1631 1632 /* The number of bytes in a double. */ 1633 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT) 1634 1635 /* Set the sizes of the core types. */ 1636 #define SHORT_TYPE_SIZE 16 1637 #define INT_TYPE_SIZE 32 1638 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) 1639 #define LONG_LONG_TYPE_SIZE 64 1640 1641 #define FLOAT_TYPE_SIZE 32 1642 #define DOUBLE_TYPE_SIZE 64 1643 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64) 1644 1645 /* Define the sizes of fixed-point types. */ 1646 #define SHORT_FRACT_TYPE_SIZE 8 1647 #define FRACT_TYPE_SIZE 16 1648 #define LONG_FRACT_TYPE_SIZE 32 1649 #define LONG_LONG_FRACT_TYPE_SIZE 64 1650 1651 #define SHORT_ACCUM_TYPE_SIZE 16 1652 #define ACCUM_TYPE_SIZE 32 1653 #define LONG_ACCUM_TYPE_SIZE 64 1654 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC 1655 doesn't support 128-bit integers for MIPS32 currently. */ 1656 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64) 1657 1658 /* long double is not a fixed mode, but the idea is that, if we 1659 support long double, we also want a 128-bit integer type. */ 1660 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE 1661 1662 /* Width in bits of a pointer. */ 1663 #ifndef POINTER_SIZE 1664 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32) 1665 #endif 1666 1667 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 1668 #define PARM_BOUNDARY BITS_PER_WORD 1669 1670 /* Allocation boundary (in *bits*) for the code of a function. */ 1671 #define FUNCTION_BOUNDARY 32 1672 1673 /* Alignment of field after `int : 0' in a structure. */ 1674 #define EMPTY_FIELD_BOUNDARY 32 1675 1676 /* Every structure's size must be a multiple of this. */ 1677 /* 8 is observed right on a DECstation and on riscos 4.02. */ 1678 #define STRUCTURE_SIZE_BOUNDARY 8 1679 1680 /* There is no point aligning anything to a rounder boundary than 1681 LONG_DOUBLE_TYPE_SIZE, unless under MSA the bigggest alignment is 1682 BITS_PER_MSA_REG. */ 1683 #define BIGGEST_ALIGNMENT \ 1684 (ISA_HAS_MSA ? BITS_PER_MSA_REG : LONG_DOUBLE_TYPE_SIZE) 1685 1686 /* All accesses must be aligned. */ 1687 #define STRICT_ALIGNMENT (!ISA_HAS_UNALIGNED_ACCESS) 1688 1689 /* Define this if you wish to imitate the way many other C compilers 1690 handle alignment of bitfields and the structures that contain 1691 them. 1692 1693 The behavior is that the type written for a bit-field (`int', 1694 `short', or other integer type) imposes an alignment for the 1695 entire structure, as if the structure really did contain an 1696 ordinary field of that type. In addition, the bit-field is placed 1697 within the structure so that it would fit within such a field, 1698 not crossing a boundary for it. 1699 1700 Thus, on most machines, a bit-field whose type is written as `int' 1701 would not cross a four-byte boundary, and would force four-byte 1702 alignment for the whole structure. (The alignment used may not 1703 be four bytes; it is controlled by the other alignment 1704 parameters.) 1705 1706 If the macro is defined, its definition should be a C expression; 1707 a nonzero value for the expression enables this behavior. */ 1708 1709 #define PCC_BITFIELD_TYPE_MATTERS 1 1710 1711 /* If defined, a C expression to compute the alignment for a static 1712 variable. TYPE is the data type, and ALIGN is the alignment that 1713 the object would ordinarily have. The value of this macro is used 1714 instead of that alignment to align the object. 1715 1716 If this macro is not defined, then ALIGN is used. 1717 1718 One use of this macro is to increase alignment of medium-size 1719 data to make it all fit in fewer cache lines. Another is to 1720 cause character arrays to be word-aligned so that `strcpy' calls 1721 that copy constants to character arrays can be done inline. */ 1722 1723 #undef DATA_ALIGNMENT 1724 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 1725 ((((ALIGN) < BITS_PER_WORD) \ 1726 && (TREE_CODE (TYPE) == ARRAY_TYPE \ 1727 || TREE_CODE (TYPE) == UNION_TYPE \ 1728 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 1729 1730 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause 1731 character arrays to be word-aligned so that `strcpy' calls that copy 1732 constants to character arrays can be done inline, and 'strcmp' can be 1733 optimised to use word loads. */ 1734 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 1735 DATA_ALIGNMENT (TYPE, ALIGN) 1736 1737 #define PAD_VARARGS_DOWN \ 1738 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD) 1739 1740 /* Define if operations between registers always perform the operation 1741 on the full register even if a narrower mode is specified. */ 1742 #define WORD_REGISTER_OPERATIONS 1 1743 1744 /* When in 64-bit mode, move insns will sign extend SImode and CCmode 1745 moves. All other references are zero extended. */ 1746 #define LOAD_EXTEND_OP(MODE) \ 1747 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \ 1748 ? SIGN_EXTEND : ZERO_EXTEND) 1749 1750 /* Define this macro if it is advisable to hold scalars in registers 1751 in a wider mode than that declared by the program. In such cases, 1752 the value is constrained to be within the bounds of the declared 1753 type, but kept valid in the wider mode. The signedness of the 1754 extension may differ from that of the type. */ 1755 1756 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1757 if (GET_MODE_CLASS (MODE) == MODE_INT \ 1758 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 1759 { \ 1760 if ((MODE) == SImode) \ 1761 (UNSIGNEDP) = 0; \ 1762 (MODE) = Pmode; \ 1763 } 1764 1765 /* Pmode is always the same as ptr_mode, but not always the same as word_mode. 1766 Extensions of pointers to word_mode must be signed. */ 1767 #define POINTERS_EXTEND_UNSIGNED false 1768 1769 /* Define if loading short immediate values into registers sign extends. */ 1770 #define SHORT_IMMEDIATES_SIGN_EXTEND 1 1771 1772 /* The [d]clz instructions have the natural values at 0. */ 1773 1774 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1775 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 1776 1777 /* Standard register usage. */ 1778 1779 /* Number of hardware registers. We have: 1780 1781 - 32 integer registers 1782 - 32 floating point registers 1783 - 8 condition code registers 1784 - 2 accumulator registers (hi and lo) 1785 - 32 registers each for coprocessors 0, 2 and 3 1786 - 4 fake registers: 1787 - ARG_POINTER_REGNUM 1788 - FRAME_POINTER_REGNUM 1789 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details) 1790 - CPRESTORE_SLOT_REGNUM 1791 - 2 dummy entries that were used at various times in the past. 1792 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE 1793 - 6 DSP control registers */ 1794 1795 #define FIRST_PSEUDO_REGISTER 188 1796 1797 /* By default, fix the kernel registers ($26 and $27), the global 1798 pointer ($28) and the stack pointer ($29). This can change 1799 depending on the command-line options. 1800 1801 Regarding coprocessor registers: without evidence to the contrary, 1802 it's best to assume that each coprocessor register has a unique 1803 use. This can be overridden, in, e.g., mips_option_override or 1804 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be 1805 inappropriate for a particular target. */ 1806 1807 #define FIXED_REGISTERS \ 1808 { \ 1809 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1810 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \ 1811 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1812 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1813 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \ 1814 /* COP0 registers */ \ 1815 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1816 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1817 /* COP2 registers */ \ 1818 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1819 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1820 /* COP3 registers */ \ 1821 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1822 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1823 /* 6 DSP accumulator registers & 6 control registers */ \ 1824 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \ 1825 } 1826 1827 1828 /* Set up this array for o32 by default. 1829 1830 Note that we don't mark $31 as a call-clobbered register. The idea is 1831 that it's really the call instructions themselves which clobber $31. 1832 We don't care what the called function does with it afterwards. 1833 1834 This approach makes it easier to implement sibcalls. Unlike normal 1835 calls, sibcalls don't clobber $31, so the register reaches the 1836 called function in tact. EPILOGUE_USES says that $31 is useful 1837 to the called function. */ 1838 1839 #define CALL_REALLY_USED_REGISTERS \ 1840 { /* General registers. */ \ 1841 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1842 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \ 1843 /* Floating-point registers. */ \ 1844 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1845 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1846 /* Others. */ \ 1847 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \ 1848 /* COP0 registers */ \ 1849 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1850 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1851 /* COP2 registers */ \ 1852 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1853 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1854 /* COP3 registers */ \ 1855 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1856 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1857 /* 6 DSP accumulator registers & 6 control registers */ \ 1858 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \ 1859 } 1860 1861 /* Internal macros to classify a register number as to whether it's a 1862 general purpose register, a floating point register, a 1863 multiply/divide register, or a status register. */ 1864 1865 #define GP_REG_FIRST 0 1866 #define GP_REG_LAST 31 1867 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) 1868 #define GP_DBX_FIRST 0 1869 #define K0_REG_NUM (GP_REG_FIRST + 26) 1870 #define K1_REG_NUM (GP_REG_FIRST + 27) 1871 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM)) 1872 1873 #define FP_REG_FIRST 32 1874 #define FP_REG_LAST 63 1875 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) 1876 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32) 1877 1878 #define MD_REG_FIRST 64 1879 #define MD_REG_LAST 65 1880 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1) 1881 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM) 1882 1883 #define MSA_REG_FIRST FP_REG_FIRST 1884 #define MSA_REG_LAST FP_REG_LAST 1885 #define MSA_REG_NUM FP_REG_NUM 1886 1887 /* The DWARF 2 CFA column which tracks the return address from a 1888 signal handler context. This means that to maintain backwards 1889 compatibility, no hard register can be assigned this column if it 1890 would need to be handled by the DWARF unwinder. */ 1891 #define DWARF_ALT_FRAME_RETURN_COLUMN 66 1892 1893 #define ST_REG_FIRST 67 1894 #define ST_REG_LAST 74 1895 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1) 1896 1897 1898 /* FIXME: renumber. */ 1899 #define COP0_REG_FIRST 80 1900 #define COP0_REG_LAST 111 1901 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1) 1902 1903 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12) 1904 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13) 1905 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14) 1906 1907 #define COP2_REG_FIRST 112 1908 #define COP2_REG_LAST 143 1909 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1) 1910 1911 #define COP3_REG_FIRST 144 1912 #define COP3_REG_LAST 175 1913 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1) 1914 1915 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */ 1916 #define ALL_COP_REG_FIRST COP0_REG_FIRST 1917 #define ALL_COP_REG_LAST COP3_REG_LAST 1918 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1) 1919 1920 #define DSP_ACC_REG_FIRST 176 1921 #define DSP_ACC_REG_LAST 181 1922 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1) 1923 1924 #define AT_REGNUM (GP_REG_FIRST + 1) 1925 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1) 1926 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST) 1927 1928 /* A few bitfield locations for the coprocessor registers. */ 1929 /* Request Interrupt Priority Level is from bit 10 to bit 15 of 1930 the cause register for the EIC interrupt mode. */ 1931 #define CAUSE_IPL 10 1932 /* COP1 Enable is at bit 29 of the status register. */ 1933 #define SR_COP1 29 1934 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */ 1935 #define SR_IPL 10 1936 /* Interrupt masks start with IM0 at bit 8 to IM7 at bit 15 of the status 1937 register. */ 1938 #define SR_IM0 8 1939 /* Exception Level is at bit 1 of the status register. */ 1940 #define SR_EXL 1 1941 /* Interrupt Enable is at bit 0 of the status register. */ 1942 #define SR_IE 0 1943 1944 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC. 1945 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG 1946 should be used instead. */ 1947 #define FPSW_REGNUM ST_REG_FIRST 1948 1949 #define GP_REG_P(REGNO) \ 1950 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) 1951 #define M16_REG_P(REGNO) \ 1952 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17) 1953 #define M16STORE_REG_P(REGNO) \ 1954 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17) 1955 #define FP_REG_P(REGNO) \ 1956 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) 1957 #define MD_REG_P(REGNO) \ 1958 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM) 1959 #define ST_REG_P(REGNO) \ 1960 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM) 1961 #define COP0_REG_P(REGNO) \ 1962 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM) 1963 #define COP2_REG_P(REGNO) \ 1964 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM) 1965 #define COP3_REG_P(REGNO) \ 1966 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM) 1967 #define ALL_COP_REG_P(REGNO) \ 1968 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM) 1969 /* Test if REGNO is one of the 6 new DSP accumulators. */ 1970 #define DSP_ACC_REG_P(REGNO) \ 1971 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM) 1972 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */ 1973 #define ACC_REG_P(REGNO) \ 1974 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO)) 1975 #define MSA_REG_P(REGNO) \ 1976 ((unsigned int) ((int) (REGNO) - MSA_REG_FIRST) < MSA_REG_NUM) 1977 1978 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) 1979 #define MSA_REG_RTX_P(X) (REG_P (X) && MSA_REG_P (REGNO (X))) 1980 1981 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used 1982 to initialize the mips16 gp pseudo register. */ 1983 #define CONST_GP_P(X) \ 1984 (GET_CODE (X) == CONST \ 1985 && GET_CODE (XEXP (X, 0)) == UNSPEC \ 1986 && XINT (XEXP (X, 0), 1) == UNSPEC_GP) 1987 1988 /* Return coprocessor number from register number. */ 1989 1990 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \ 1991 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \ 1992 : COP3_REG_P (REGNO) ? '3' : '?') 1993 1994 1995 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ 1996 mips_hard_regno_rename_ok (OLD_REG, NEW_REG) 1997 1998 /* Select a register mode required for caller save of hard regno REGNO. */ 1999 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 2000 mips_hard_regno_caller_save_mode (REGNO, NREGS, MODE) 2001 2002 /* Register to use for pushing function arguments. */ 2003 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29) 2004 2005 /* These two registers don't really exist: they get eliminated to either 2006 the stack or hard frame pointer. */ 2007 #define ARG_POINTER_REGNUM 77 2008 #define FRAME_POINTER_REGNUM 78 2009 2010 /* $30 is not available on the mips16, so we use $17 as the frame 2011 pointer. */ 2012 #define HARD_FRAME_POINTER_REGNUM \ 2013 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30) 2014 2015 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 2016 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 2017 2018 /* Register in which static-chain is passed to a function. */ 2019 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15) 2020 2021 /* Registers used as temporaries in prologue/epilogue code: 2022 2023 - If a MIPS16 PIC function needs access to _gp, it first loads 2024 the value into MIPS16_PIC_TEMP and then copies it to $gp. 2025 2026 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary 2027 register. The register must not conflict with MIPS16_PIC_TEMP. 2028 2029 - If we aren't generating MIPS16 code, the prologue can also use 2030 MIPS_PROLOGUE_TEMP2 as a general temporary register. 2031 2032 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary 2033 register. 2034 2035 If we're generating MIPS16 code, these registers must come from the 2036 core set of 8. The prologue registers mustn't conflict with any 2037 incoming arguments, the static chain pointer, or the frame pointer. 2038 The epilogue temporary mustn't conflict with the return registers, 2039 the PIC call register ($25), the frame pointer, the EH stack adjustment, 2040 or the EH data registers. 2041 2042 If we're generating interrupt handlers, we use K0 as a temporary register 2043 in prologue/epilogue code. */ 2044 2045 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2) 2046 #define MIPS_PROLOGUE_TEMP_REGNUM \ 2047 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3) 2048 #define MIPS_PROLOGUE_TEMP2_REGNUM \ 2049 (TARGET_MIPS16 \ 2050 ? (gcc_unreachable (), INVALID_REGNUM) \ 2051 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12) 2052 #define MIPS_EPILOGUE_TEMP_REGNUM \ 2053 (cfun->machine->interrupt_handler_p \ 2054 ? K0_REG_NUM \ 2055 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8)) 2056 2057 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM) 2058 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM) 2059 #define MIPS_PROLOGUE_TEMP2(MODE) \ 2060 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM) 2061 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM) 2062 2063 /* Define this macro if it is as good or better to call a constant 2064 function address than to call an address kept in a register. */ 2065 #define NO_FUNCTION_CSE 1 2066 2067 /* The ABI-defined global pointer. Sometimes we use a different 2068 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */ 2069 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28) 2070 2071 /* We normally use $28 as the global pointer. However, when generating 2072 n32/64 PIC, it is better for leaf functions to use a call-clobbered 2073 register instead. They can then avoid saving and restoring $28 2074 and perhaps avoid using a frame at all. 2075 2076 When a leaf function uses something other than $28, mips_expand_prologue 2077 will modify pic_offset_table_rtx in place. Take the register number 2078 from there after reload. */ 2079 #define PIC_OFFSET_TABLE_REGNUM \ 2080 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM) 2081 2082 /* Define the classes of registers for register constraints in the 2083 machine description. Also define ranges of constants. 2084 2085 One of the classes must always be named ALL_REGS and include all hard regs. 2086 If there is more than one class, another class must be named NO_REGS 2087 and contain no registers. 2088 2089 The name GENERAL_REGS must be the name of a class (or an alias for 2090 another name such as ALL_REGS). This is the class of registers 2091 that is allowed by "g" or "r" in a register constraint. 2092 Also, registers outside this class are allocated only when 2093 instructions express preferences for them. 2094 2095 The classes must be numbered in nondecreasing order; that is, 2096 a larger-numbered class must never be contained completely 2097 in a smaller-numbered class. 2098 2099 For any two classes, it is very desirable that there be another 2100 class that represents their union. */ 2101 2102 enum reg_class 2103 { 2104 NO_REGS, /* no registers in set */ 2105 M16_STORE_REGS, /* microMIPS store registers */ 2106 M16_REGS, /* mips16 directly accessible registers */ 2107 M16_SP_REGS, /* mips16 + $sp */ 2108 T_REG, /* mips16 T register ($24) */ 2109 M16_T_REGS, /* mips16 registers plus T register */ 2110 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */ 2111 V1_REG, /* Register $v1 ($3) used for TLS access. */ 2112 SPILL_REGS, /* All but $sp and call preserved regs are in here */ 2113 LEA_REGS, /* Every GPR except $25 */ 2114 GR_REGS, /* integer registers */ 2115 FP_REGS, /* floating point registers */ 2116 MD0_REG, /* first multiply/divide register */ 2117 MD1_REG, /* second multiply/divide register */ 2118 MD_REGS, /* multiply/divide registers (hi/lo) */ 2119 COP0_REGS, /* generic coprocessor classes */ 2120 COP2_REGS, 2121 COP3_REGS, 2122 ST_REGS, /* status registers (fp status) */ 2123 DSP_ACC_REGS, /* DSP accumulator registers */ 2124 ACC_REGS, /* Hi/Lo and DSP accumulator registers */ 2125 FRAME_REGS, /* $arg and $frame */ 2126 GR_AND_MD0_REGS, /* union classes */ 2127 GR_AND_MD1_REGS, 2128 GR_AND_MD_REGS, 2129 GR_AND_ACC_REGS, 2130 ALL_REGS, /* all registers */ 2131 LIM_REG_CLASSES /* max value + 1 */ 2132 }; 2133 2134 #define N_REG_CLASSES (int) LIM_REG_CLASSES 2135 2136 #define GENERAL_REGS GR_REGS 2137 2138 /* An initializer containing the names of the register classes as C 2139 string constants. These names are used in writing some of the 2140 debugging dumps. */ 2141 2142 #define REG_CLASS_NAMES \ 2143 { \ 2144 "NO_REGS", \ 2145 "M16_STORE_REGS", \ 2146 "M16_REGS", \ 2147 "M16_SP_REGS", \ 2148 "T_REG", \ 2149 "M16_T_REGS", \ 2150 "PIC_FN_ADDR_REG", \ 2151 "V1_REG", \ 2152 "SPILL_REGS", \ 2153 "LEA_REGS", \ 2154 "GR_REGS", \ 2155 "FP_REGS", \ 2156 "MD0_REG", \ 2157 "MD1_REG", \ 2158 "MD_REGS", \ 2159 /* coprocessor registers */ \ 2160 "COP0_REGS", \ 2161 "COP2_REGS", \ 2162 "COP3_REGS", \ 2163 "ST_REGS", \ 2164 "DSP_ACC_REGS", \ 2165 "ACC_REGS", \ 2166 "FRAME_REGS", \ 2167 "GR_AND_MD0_REGS", \ 2168 "GR_AND_MD1_REGS", \ 2169 "GR_AND_MD_REGS", \ 2170 "GR_AND_ACC_REGS", \ 2171 "ALL_REGS" \ 2172 } 2173 2174 /* An initializer containing the contents of the register classes, 2175 as integers which are bit masks. The Nth integer specifies the 2176 contents of class N. The way the integer MASK is interpreted is 2177 that register R is in the class if `MASK & (1 << R)' is 1. 2178 2179 When the machine has more than 32 registers, an integer does not 2180 suffice. Then the integers are replaced by sub-initializers, 2181 braced groupings containing several integers. Each 2182 sub-initializer must be suitable as an initializer for the type 2183 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ 2184 2185 #define REG_CLASS_CONTENTS \ 2186 { \ 2187 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 2188 { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \ 2189 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \ 2190 { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_SP_REGS */ \ 2191 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \ 2192 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \ 2193 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \ 2194 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \ 2195 { 0x0303fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SPILL_REGS */ \ 2196 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \ 2197 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \ 2198 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \ 2199 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \ 2200 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \ 2201 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \ 2202 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \ 2203 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \ 2204 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \ 2205 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \ 2206 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \ 2207 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \ 2208 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \ 2209 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \ 2210 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \ 2211 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \ 2212 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \ 2213 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \ 2214 } 2215 2216 2217 /* A C expression whose value is a register class containing hard 2218 register REGNO. In general there is more that one such class; 2219 choose a class which is "minimal", meaning that no smaller class 2220 also contains the register. */ 2221 2222 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ] 2223 2224 /* A macro whose definition is the name of the class to which a 2225 valid base register must belong. A base register is one used in 2226 an address which is the register value plus a displacement. */ 2227 2228 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_SP_REGS : GR_REGS) 2229 2230 /* A macro whose definition is the name of the class to which a 2231 valid index register must belong. An index register is one used 2232 in an address where its value is either multiplied by a scale 2233 factor or added to another register (as well as added to a 2234 displacement). */ 2235 2236 #define INDEX_REG_CLASS NO_REGS 2237 2238 /* We generally want to put call-clobbered registers ahead of 2239 call-saved ones. (IRA expects this.) */ 2240 2241 #define REG_ALLOC_ORDER \ 2242 { /* Accumulator registers. When GPRs and accumulators have equal \ 2243 cost, we generally prefer to use accumulators. For example, \ 2244 a division of multiplication result is better allocated to LO, \ 2245 so that we put the MFLO at the point of use instead of at the \ 2246 point of definition. It's also needed if we're to take advantage \ 2247 of the extra accumulators available with -mdspr2. In some cases, \ 2248 it can also help to reduce register pressure. */ \ 2249 64, 65,176,177,178,179,180,181, \ 2250 /* Call-clobbered GPRs. */ \ 2251 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 2252 24, 25, 31, \ 2253 /* The global pointer. This is call-clobbered for o32 and o64 \ 2254 abicalls, call-saved for n32 and n64 abicalls, and a program \ 2255 invariant otherwise. Putting it between the call-clobbered \ 2256 and call-saved registers should cope with all eventualities. */ \ 2257 28, \ 2258 /* Call-saved GPRs. */ \ 2259 16, 17, 18, 19, 20, 21, 22, 23, 30, \ 2260 /* GPRs that can never be exposed to the register allocator. */ \ 2261 0, 26, 27, 29, \ 2262 /* Call-clobbered FPRs. */ \ 2263 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 2264 48, 49, 50, 51, \ 2265 /* FPRs that are usually call-saved. The odd ones are actually \ 2266 call-clobbered for n32, but listing them ahead of the even \ 2267 registers might encourage the register allocator to fragment \ 2268 the available FPR pairs. We need paired FPRs to store long \ 2269 doubles, so it isn't clear that using a different order \ 2270 for n32 would be a win. */ \ 2271 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ 2272 /* None of the remaining classes have defined call-saved \ 2273 registers. */ \ 2274 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ 2275 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \ 2276 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \ 2277 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \ 2278 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \ 2279 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \ 2280 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \ 2281 182,183,184,185,186,187 \ 2282 } 2283 2284 /* True if VALUE is an unsigned 6-bit number. */ 2285 2286 #define UIMM6_OPERAND(VALUE) \ 2287 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0) 2288 2289 /* True if VALUE is a signed 10-bit number. */ 2290 2291 #define IMM10_OPERAND(VALUE) \ 2292 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400) 2293 2294 /* True if VALUE is a signed 16-bit number. */ 2295 2296 #define SMALL_OPERAND(VALUE) \ 2297 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000) 2298 2299 /* True if VALUE is an unsigned 16-bit number. */ 2300 2301 #define SMALL_OPERAND_UNSIGNED(VALUE) \ 2302 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0) 2303 2304 /* True if VALUE can be loaded into a register using LUI. */ 2305 2306 #define LUI_OPERAND(VALUE) \ 2307 (((VALUE) | 0x7fff0000) == 0x7fff0000 \ 2308 || ((unsigned HOST_WIDE_INT) (VALUE) | 0x7fff0000) + 0x10000 == 0) 2309 2310 /* Return a value X with the low 16 bits clear, and such that 2311 VALUE - X is a signed 16-bit value. */ 2312 2313 #define CONST_HIGH_PART(VALUE) \ 2314 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff) 2315 2316 #define CONST_LOW_PART(VALUE) \ 2317 ((VALUE) - CONST_HIGH_PART (VALUE)) 2318 2319 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X)) 2320 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X)) 2321 #define LUI_INT(X) LUI_OPERAND (INTVAL (X)) 2322 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047)) 2323 #define MIPS_9BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -256, 255)) 2324 2325 /* The HI and LO registers can only be reloaded via the general 2326 registers. Condition code registers can only be loaded to the 2327 general registers, and from the floating point registers. */ 2328 2329 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 2330 mips_secondary_reload_class (CLASS, MODE, X, true) 2331 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 2332 mips_secondary_reload_class (CLASS, MODE, X, false) 2333 2334 /* Return the maximum number of consecutive registers 2335 needed to represent mode MODE in a register of class CLASS. */ 2336 2337 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE) 2338 2339 /* Stack layout; function entry, exit and calling. */ 2340 2341 #define STACK_GROWS_DOWNWARD 1 2342 2343 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ 2344 || (flag_sanitize & SANITIZE_ADDRESS) != 0) 2345 2346 /* Size of the area allocated in the frame to save the GP. */ 2347 2348 #define MIPS_GP_SAVE_AREA_SIZE \ 2349 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0) 2350 2351 #define RETURN_ADDR_RTX mips_return_addr 2352 2353 /* Mask off the MIPS16 ISA bit in unwind addresses. 2354 2355 The reason for this is a little subtle. When unwinding a call, 2356 we are given the call's return address, which on most targets 2357 is the address of the following instruction. However, what we 2358 actually want to find is the EH region for the call itself. 2359 The target-independent unwind code therefore searches for "RA - 1". 2360 2361 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address. 2362 RA - 1 is therefore the real (even-valued) start of the return 2363 instruction. EH region labels are usually odd-valued MIPS16 symbols 2364 too, so a search for an even address within a MIPS16 region would 2365 usually work. 2366 2367 However, there is an exception. If the end of an EH region is also 2368 the end of a function, the end label is allowed to be even. This is 2369 necessary because a following non-MIPS16 function may also need EH 2370 information for its first instruction. 2371 2372 Thus a MIPS16 region may be terminated by an ISA-encoded or a 2373 non-ISA-encoded address. This probably isn't ideal, but it is 2374 the traditional (legacy) behavior. It is therefore only safe 2375 to search MIPS EH regions for an _odd-valued_ address. 2376 2377 Masking off the ISA bit means that the target-independent code 2378 will search for "(RA & -2) - 1", which is guaranteed to be odd. */ 2379 #define MASK_RETURN_ADDR GEN_INT (-2) 2380 2381 2382 /* Similarly, don't use the least-significant bit to tell pointers to 2383 code from vtable index. */ 2384 2385 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 2386 2387 /* The eliminations to $17 are only used for mips16 code. See the 2388 definition of HARD_FRAME_POINTER_REGNUM. */ 2389 2390 #define ELIMINABLE_REGS \ 2391 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 2392 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \ 2393 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \ 2394 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 2395 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \ 2396 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}} 2397 2398 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 2399 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO)) 2400 2401 /* Allocate stack space for arguments at the beginning of each function. */ 2402 #define ACCUMULATE_OUTGOING_ARGS 1 2403 2404 /* The argument pointer always points to the first argument. */ 2405 #define FIRST_PARM_OFFSET(FNDECL) 0 2406 2407 /* o32 and o64 reserve stack space for all argument registers. */ 2408 #define REG_PARM_STACK_SPACE(FNDECL) \ 2409 (TARGET_OLDABI \ 2410 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \ 2411 : 0) 2412 2413 /* Define this if it is the responsibility of the caller to 2414 allocate the area reserved for arguments passed in registers. 2415 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect 2416 of this macro is to determine whether the space is included in 2417 `crtl->outgoing_args_size'. */ 2418 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 2419 2420 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64) 2421 2422 /* Symbolic macros for the registers used to return integer and floating 2423 point values. */ 2424 2425 #define GP_RETURN (GP_REG_FIRST + 2) 2426 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0)) 2427 2428 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8) 2429 2430 /* Symbolic macros for the first/last argument registers. */ 2431 2432 #define GP_ARG_FIRST (GP_REG_FIRST + 4) 2433 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 2434 #define FP_ARG_FIRST (FP_REG_FIRST + 12) 2435 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 2436 2437 /* True if MODE is vector and supported in a MSA vector register. */ 2438 #define MSA_SUPPORTED_MODE_P(MODE) \ 2439 (ISA_HAS_MSA \ 2440 && GET_MODE_SIZE (MODE) == UNITS_PER_MSA_REG \ 2441 && (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT \ 2442 || GET_MODE_CLASS (MODE) == MODE_VECTOR_FLOAT)) 2443 2444 /* Temporary register that is used when restoring $gp after a call. $4 and $5 2445 are used for returning complex double values in soft-float code, so $6 is the 2446 first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use 2447 $gp itself as the temporary. */ 2448 #define POST_CALL_TMP_REG \ 2449 (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM) 2450 2451 /* 1 if N is a possible register number for function argument passing. 2452 We have no FP argument registers when soft-float. Special handling 2453 is required for O32 where only even numbered registers are used for 2454 O32-FPXX and O32-FP64. */ 2455 2456 #define FUNCTION_ARG_REGNO_P(N) \ 2457 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \ 2458 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \ 2459 && (mips_abi != ABI_32 \ 2460 || TARGET_FLOAT32 \ 2461 || ((N) % 2 == 0)))) \ 2462 && !fixed_regs[N]) 2463 2464 /* This structure has to cope with two different argument allocation 2465 schemes. Most MIPS ABIs view the arguments as a structure, of which 2466 the first N words go in registers and the rest go on the stack. If I 2467 < N, the Ith word might go in Ith integer argument register or in a 2468 floating-point register. For these ABIs, we only need to remember 2469 the offset of the current argument into the structure. 2470 2471 The EABI instead allocates the integer and floating-point arguments 2472 separately. The first N words of FP arguments go in FP registers, 2473 the rest go on the stack. Likewise, the first N words of the other 2474 arguments go in integer registers, and the rest go on the stack. We 2475 need to maintain three counts: the number of integer registers used, 2476 the number of floating-point registers used, and the number of words 2477 passed on the stack. 2478 2479 We could keep separate information for the two ABIs (a word count for 2480 the standard ABIs, and three separate counts for the EABI). But it 2481 seems simpler to view the standard ABIs as forms of EABI that do not 2482 allocate floating-point registers. 2483 2484 So for the standard ABIs, the first N words are allocated to integer 2485 registers, and mips_function_arg decides on an argument-by-argument 2486 basis whether that argument should really go in an integer register, 2487 or in a floating-point one. */ 2488 2489 typedef struct mips_args { 2490 /* Always true for varargs functions. Otherwise true if at least 2491 one argument has been passed in an integer register. */ 2492 int gp_reg_found; 2493 2494 /* The number of arguments seen so far. */ 2495 unsigned int arg_number; 2496 2497 /* The number of integer registers used so far. For all ABIs except 2498 EABI, this is the number of words that have been added to the 2499 argument structure, limited to MAX_ARGS_IN_REGISTERS. */ 2500 unsigned int num_gprs; 2501 2502 /* For EABI, the number of floating-point registers used so far. */ 2503 unsigned int num_fprs; 2504 2505 /* The number of words passed on the stack. */ 2506 unsigned int stack_words; 2507 2508 /* On the mips16, we need to keep track of which floating point 2509 arguments were passed in general registers, but would have been 2510 passed in the FP regs if this were a 32-bit function, so that we 2511 can move them to the FP regs if we wind up calling a 32-bit 2512 function. We record this information in fp_code, encoded in base 2513 four. A zero digit means no floating point argument, a one digit 2514 means an SFmode argument, and a two digit means a DFmode argument, 2515 and a three digit is not used. The low order digit is the first 2516 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by 2517 an SFmode argument. ??? A more sophisticated approach will be 2518 needed if MIPS_ABI != ABI_32. */ 2519 int fp_code; 2520 2521 /* True if the function has a prototype. */ 2522 int prototype; 2523 } CUMULATIVE_ARGS; 2524 2525 /* Initialize a variable CUM of type CUMULATIVE_ARGS 2526 for a call to a function whose data type is FNTYPE. 2527 For a library call, FNTYPE is 0. */ 2528 2529 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 2530 mips_init_cumulative_args (&CUM, FNTYPE) 2531 2532 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 2533 (mips_pad_reg_upward (MODE, TYPE) ? PAD_UPWARD : PAD_DOWNWARD) 2534 2535 /* True if using EABI and varargs can be passed in floating-point 2536 registers. Under these conditions, we need a more complex form 2537 of va_list, which tracks GPR, FPR and stack arguments separately. */ 2538 #define EABI_FLOAT_VARARGS_P \ 2539 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE) 2540 2541 2542 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO) 2543 2544 /* Treat LOC as a byte offset from the stack pointer and round it up 2545 to the next fully-aligned offset. */ 2546 #define MIPS_STACK_ALIGN(LOC) \ 2547 (TARGET_NEWABI ? ROUND_UP ((LOC), 16) : ROUND_UP ((LOC), 8)) 2548 2549 2550 /* Output assembler code to FILE to increment profiler label # LABELNO 2551 for profiling a function entry. */ 2552 2553 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE)) 2554 2555 /* The profiler preserves all interesting registers, including $31. */ 2556 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false 2557 2558 /* No mips port has ever used the profiler counter word, so don't emit it 2559 or the label for it. */ 2560 2561 #define NO_PROFILE_COUNTERS 1 2562 2563 /* Define this macro if the code for function profiling should come 2564 before the function prologue. Normally, the profiling code comes 2565 after. */ 2566 2567 /* #define PROFILE_BEFORE_PROLOGUE */ 2568 2569 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 2570 the stack pointer does not matter. The value is tested only in 2571 functions that have frame pointers. 2572 No definition is equivalent to always zero. */ 2573 2574 #define EXIT_IGNORE_STACK 1 2575 2576 2577 /* Trampolines are a block of code followed by two pointers. */ 2578 2579 #define TRAMPOLINE_SIZE \ 2580 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2) 2581 2582 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two 2583 pointers from a single LUI base. */ 2584 2585 #define TRAMPOLINE_ALIGNMENT 64 2586 2587 /* mips_trampoline_init calls this library function to flush 2588 program and data caches. */ 2589 2590 #ifndef CACHE_FLUSH_FUNC 2591 #define CACHE_FLUSH_FUNC "_flush_cache" 2592 #endif 2593 2594 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \ 2595 /* Flush both caches. We need to flush the data cache in case \ 2596 the system has a write-back cache. */ \ 2597 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \ 2598 LCT_NORMAL, VOIDmode, ADDR, Pmode, SIZE, Pmode, \ 2599 GEN_INT (3), TYPE_MODE (integer_type_node)) 2600 2601 2602 /* Addressing modes, and classification of registers for them. */ 2603 2604 #define REGNO_OK_FOR_INDEX_P(REGNO) 0 2605 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 2606 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1) 2607 2608 /* Maximum number of registers that can appear in a valid memory address. */ 2609 2610 #define MAX_REGS_PER_ADDRESS 1 2611 2612 /* Check for constness inline but use mips_legitimate_address_p 2613 to check whether a constant really is an address. */ 2614 2615 #define CONSTANT_ADDRESS_P(X) \ 2616 (CONSTANT_P (X) && memory_address_p (SImode, X)) 2617 2618 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means 2619 'the start of the function that this code is output in'. */ 2620 2621 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 2622 do { \ 2623 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ 2624 asm_fprintf ((FILE), "%U%s", \ 2625 XSTR (XEXP (DECL_RTL (current_function_decl), \ 2626 0), 0)); \ 2627 else \ 2628 asm_fprintf ((FILE), "%U%s", (NAME)); \ 2629 } while (0) 2630 2631 /* Flag to mark a function decl symbol that requires a long call. */ 2632 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0) 2633 #define SYMBOL_REF_LONG_CALL_P(X) \ 2634 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0) 2635 2636 /* This flag marks functions that cannot be lazily bound. */ 2637 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1) 2638 #define SYMBOL_REF_BIND_NOW_P(RTX) \ 2639 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0) 2640 2641 /* True if we're generating a form of MIPS16 code in which jump tables 2642 are stored in the text section and encoded as 16-bit PC-relative 2643 offsets. This is only possible when general text loads are allowed, 2644 since the table access itself will be an "lh" instruction. If the 2645 PC-relative offsets grow too large, 32-bit offsets are used instead. */ 2646 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS 2647 2648 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES 2649 2650 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode) 2651 2652 /* Only use short offsets if their range will not overflow. */ 2653 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \ 2654 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \ 2655 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \ 2656 : SImode) 2657 2658 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES 2659 2660 /* Define this as 1 if `char' should by default be signed; else as 0. */ 2661 #ifndef DEFAULT_SIGNED_CHAR 2662 #define DEFAULT_SIGNED_CHAR 1 2663 #endif 2664 2665 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets, 2666 we generally don't want to use them for copying arbitrary data. 2667 A single N-word move is usually the same cost as N single-word moves. */ 2668 #define MOVE_MAX UNITS_PER_WORD 2669 /* We don't modify it for MSA as it is only used by the classic reload. */ 2670 #define MAX_MOVE_MAX 8 2671 2672 /* Define this macro as a C expression which is nonzero if 2673 accessing less than a word of memory (i.e. a `char' or a 2674 `short') is no faster than accessing a word of memory, i.e., if 2675 such access require more than one instruction or if there is no 2676 difference in cost between byte and (aligned) word loads. 2677 2678 On RISC machines, it tends to generate better code to define 2679 this as 1, since it avoids making a QI or HI mode register. 2680 2681 But, generating word accesses for -mips16 is generally bad as shifts 2682 (often extended) would be needed for byte accesses. */ 2683 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16) 2684 2685 /* Standard MIPS integer shifts truncate the shift amount to the 2686 width of the shifted operand. However, Loongson MMI shifts 2687 do not truncate the shift amount at all. */ 2688 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_MMI) 2689 2690 2691 /* Specify the machine mode that pointers have. 2692 After generation of rtl, the compiler makes no further distinction 2693 between pointers and any other objects of this machine mode. */ 2694 2695 #ifndef Pmode 2696 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode) 2697 #endif 2698 2699 /* Give call MEMs SImode since it is the "most permissive" mode 2700 for both 32-bit and 64-bit targets. */ 2701 2702 #define FUNCTION_MODE SImode 2703 2704 2705 /* We allocate $fcc registers by hand and can't cope with moves of 2706 CCmode registers to and from pseudos (or memory). */ 2707 #define AVOID_CCMODE_COPIES 2708 2709 /* A C expression for the cost of a branch instruction. A value of 2710 1 is the default; other values are interpreted relative to that. */ 2711 2712 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost 2713 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 2714 2715 /* The MIPS port has several functions that return an instruction count. 2716 Multiplying the count by this value gives the number of bytes that 2717 the instructions occupy. */ 2718 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4) 2719 2720 /* The length of a NOP in bytes. */ 2721 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4) 2722 2723 /* If defined, modifies the length assigned to instruction INSN as a 2724 function of the context in which it is used. LENGTH is an lvalue 2725 that contains the initially computed length of the insn and should 2726 be updated with the correct length of the insn. */ 2727 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ 2728 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH))) 2729 2730 /* Return the asm template for a non-MIPS16 conditional branch instruction. 2731 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for 2732 its operands. */ 2733 #define MIPS_BRANCH(OPCODE, OPERANDS) \ 2734 "%*" OPCODE "%?\t" OPERANDS "%/" 2735 2736 #define MIPS_BRANCH_C(OPCODE, OPERANDS) \ 2737 "%*" OPCODE "%:\t" OPERANDS 2738 2739 /* Return an asm string that forces INSN to be treated as an absolute 2740 J or JAL instruction instead of an assembler macro. */ 2741 #define MIPS_ABSOLUTE_JUMP(INSN) \ 2742 (TARGET_ABICALLS_PIC2 \ 2743 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \ 2744 : INSN) 2745 2746 2747 /* Control the assembler format that we output. */ 2748 2749 /* Output to assembler file text saying following lines 2750 may contain character constants, extra white space, comments, etc. */ 2751 2752 #ifndef ASM_APP_ON 2753 #define ASM_APP_ON " #APP\n" 2754 #endif 2755 2756 /* Output to assembler file text saying following lines 2757 no longer contain unusual constructs. */ 2758 2759 #ifndef ASM_APP_OFF 2760 #define ASM_APP_OFF " #NO_APP\n" 2761 #endif 2762 2763 #define REGISTER_NAMES \ 2764 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \ 2765 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ 2766 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ 2767 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \ 2768 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \ 2769 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ 2770 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \ 2771 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \ 2772 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \ 2773 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \ 2774 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \ 2775 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \ 2776 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \ 2777 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \ 2778 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \ 2779 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \ 2780 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \ 2781 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \ 2782 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \ 2783 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \ 2784 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \ 2785 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \ 2786 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \ 2787 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" } 2788 2789 /* List the "software" names for each register. Also list the numerical 2790 names for $fp and $sp. */ 2791 2792 #define ADDITIONAL_REGISTER_NAMES \ 2793 { \ 2794 { "$29", 29 + GP_REG_FIRST }, \ 2795 { "$30", 30 + GP_REG_FIRST }, \ 2796 { "at", 1 + GP_REG_FIRST }, \ 2797 { "v0", 2 + GP_REG_FIRST }, \ 2798 { "v1", 3 + GP_REG_FIRST }, \ 2799 { "a0", 4 + GP_REG_FIRST }, \ 2800 { "a1", 5 + GP_REG_FIRST }, \ 2801 { "a2", 6 + GP_REG_FIRST }, \ 2802 { "a3", 7 + GP_REG_FIRST }, \ 2803 { "t0", 8 + GP_REG_FIRST }, \ 2804 { "t1", 9 + GP_REG_FIRST }, \ 2805 { "t2", 10 + GP_REG_FIRST }, \ 2806 { "t3", 11 + GP_REG_FIRST }, \ 2807 { "t4", 12 + GP_REG_FIRST }, \ 2808 { "t5", 13 + GP_REG_FIRST }, \ 2809 { "t6", 14 + GP_REG_FIRST }, \ 2810 { "t7", 15 + GP_REG_FIRST }, \ 2811 { "s0", 16 + GP_REG_FIRST }, \ 2812 { "s1", 17 + GP_REG_FIRST }, \ 2813 { "s2", 18 + GP_REG_FIRST }, \ 2814 { "s3", 19 + GP_REG_FIRST }, \ 2815 { "s4", 20 + GP_REG_FIRST }, \ 2816 { "s5", 21 + GP_REG_FIRST }, \ 2817 { "s6", 22 + GP_REG_FIRST }, \ 2818 { "s7", 23 + GP_REG_FIRST }, \ 2819 { "t8", 24 + GP_REG_FIRST }, \ 2820 { "t9", 25 + GP_REG_FIRST }, \ 2821 { "k0", 26 + GP_REG_FIRST }, \ 2822 { "k1", 27 + GP_REG_FIRST }, \ 2823 { "gp", 28 + GP_REG_FIRST }, \ 2824 { "sp", 29 + GP_REG_FIRST }, \ 2825 { "fp", 30 + GP_REG_FIRST }, \ 2826 { "ra", 31 + GP_REG_FIRST }, \ 2827 { "$w0", 0 + FP_REG_FIRST }, \ 2828 { "$w1", 1 + FP_REG_FIRST }, \ 2829 { "$w2", 2 + FP_REG_FIRST }, \ 2830 { "$w3", 3 + FP_REG_FIRST }, \ 2831 { "$w4", 4 + FP_REG_FIRST }, \ 2832 { "$w5", 5 + FP_REG_FIRST }, \ 2833 { "$w6", 6 + FP_REG_FIRST }, \ 2834 { "$w7", 7 + FP_REG_FIRST }, \ 2835 { "$w8", 8 + FP_REG_FIRST }, \ 2836 { "$w9", 9 + FP_REG_FIRST }, \ 2837 { "$w10", 10 + FP_REG_FIRST }, \ 2838 { "$w11", 11 + FP_REG_FIRST }, \ 2839 { "$w12", 12 + FP_REG_FIRST }, \ 2840 { "$w13", 13 + FP_REG_FIRST }, \ 2841 { "$w14", 14 + FP_REG_FIRST }, \ 2842 { "$w15", 15 + FP_REG_FIRST }, \ 2843 { "$w16", 16 + FP_REG_FIRST }, \ 2844 { "$w17", 17 + FP_REG_FIRST }, \ 2845 { "$w18", 18 + FP_REG_FIRST }, \ 2846 { "$w19", 19 + FP_REG_FIRST }, \ 2847 { "$w20", 20 + FP_REG_FIRST }, \ 2848 { "$w21", 21 + FP_REG_FIRST }, \ 2849 { "$w22", 22 + FP_REG_FIRST }, \ 2850 { "$w23", 23 + FP_REG_FIRST }, \ 2851 { "$w24", 24 + FP_REG_FIRST }, \ 2852 { "$w25", 25 + FP_REG_FIRST }, \ 2853 { "$w26", 26 + FP_REG_FIRST }, \ 2854 { "$w27", 27 + FP_REG_FIRST }, \ 2855 { "$w28", 28 + FP_REG_FIRST }, \ 2856 { "$w29", 29 + FP_REG_FIRST }, \ 2857 { "$w30", 30 + FP_REG_FIRST }, \ 2858 { "$w31", 31 + FP_REG_FIRST } \ 2859 } 2860 2861 #define DBR_OUTPUT_SEQEND(STREAM) \ 2862 do \ 2863 { \ 2864 /* Undo the effect of '%*'. */ \ 2865 mips_pop_asm_switch (&mips_nomacro); \ 2866 mips_pop_asm_switch (&mips_noreorder); \ 2867 /* Emit a blank line after the delay slot for emphasis. */ \ 2868 fputs ("\n", STREAM); \ 2869 } \ 2870 while (0) 2871 2872 /* The MIPS implementation uses some labels for its own purpose. The 2873 following lists what labels are created, and are all formed by the 2874 pattern $L[a-z].*. The machine independent portion of GCC creates 2875 labels matching: $L[A-Z][0-9]+ and $L[0-9]+. 2876 2877 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt. 2878 $Lb[0-9]+ Begin blocks for MIPS debug support 2879 $Lc[0-9]+ Label for use in s<xx> operation. 2880 $Le[0-9]+ End blocks for MIPS debug support */ 2881 2882 #undef ASM_DECLARE_OBJECT_NAME 2883 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ 2884 mips_declare_object (STREAM, NAME, "", ":\n") 2885 2886 /* Globalizing directive for a label. */ 2887 #define GLOBAL_ASM_OP "\t.globl\t" 2888 2889 /* This says how to define a global common symbol. */ 2890 2891 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common 2892 2893 /* This says how to define a local common symbol (i.e., not visible to 2894 linker). */ 2895 2896 #ifndef ASM_OUTPUT_ALIGNED_LOCAL 2897 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \ 2898 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false) 2899 #endif 2900 2901 /* This says how to output an external. It would be possible not to 2902 output anything and let undefined symbol become external. However 2903 the assembler uses length information on externals to allocate in 2904 data/sdata bss/sbss, thereby saving exec time. */ 2905 2906 #undef ASM_OUTPUT_EXTERNAL 2907 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \ 2908 mips_output_external(STREAM,DECL,NAME) 2909 2910 /* This is how to declare a function name. The actual work of 2911 emitting the label is moved to function_prologue, so that we can 2912 get the line number correctly emitted before the .ent directive, 2913 and after any .file directives. Define as empty so that the function 2914 is not declared before the .ent directive elsewhere. */ 2915 2916 #undef ASM_DECLARE_FUNCTION_NAME 2917 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) 2918 2919 /* This is how to store into the string LABEL 2920 the symbol_ref name of an internal numbered label where 2921 PREFIX is the class of label and NUM is the number within the class. 2922 This is suitable for output with `assemble_name'. */ 2923 2924 #undef ASM_GENERATE_INTERNAL_LABEL 2925 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 2926 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) 2927 2928 /* Print debug labels as "foo = ." rather than "foo:" because they should 2929 represent a byte pointer rather than an ISA-encoded address. This is 2930 particularly important for code like: 2931 2932 $LFBxxx = . 2933 .cfi_startproc 2934 ... 2935 .section .gcc_except_table,... 2936 ... 2937 .uleb128 foo-$LFBxxx 2938 2939 The .uleb128 requies $LFBxxx to match the FDE start address, which is 2940 likewise a byte pointer rather than an ISA-encoded address. 2941 2942 At the time of writing, this hook is not used for the function end 2943 label: 2944 2945 $LFExxx: 2946 .end foo 2947 2948 But this doesn't matter, because GAS doesn't treat a pre-.end label 2949 as a MIPS16 one anyway. */ 2950 2951 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \ 2952 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM) 2953 2954 /* This is how to output an element of a case-vector that is absolute. */ 2955 2956 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 2957 fprintf (STREAM, "\t%s\t%sL%d\n", \ 2958 ptr_mode == DImode ? ".dword" : ".word", \ 2959 LOCAL_LABEL_PREFIX, \ 2960 VALUE) 2961 2962 /* This is how to output an element of a case-vector. We can make the 2963 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word 2964 is supported. */ 2965 2966 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 2967 do { \ 2968 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \ 2969 { \ 2970 if (GET_MODE (BODY) == HImode) \ 2971 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \ 2972 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ 2973 else \ 2974 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \ 2975 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ 2976 } \ 2977 else if (TARGET_GPWORD) \ 2978 fprintf (STREAM, "\t%s\t%sL%d\n", \ 2979 ptr_mode == DImode ? ".gpdword" : ".gpword", \ 2980 LOCAL_LABEL_PREFIX, VALUE); \ 2981 else if (TARGET_RTP_PIC) \ 2982 { \ 2983 /* Make the entry relative to the start of the function. */ \ 2984 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \ 2985 fprintf (STREAM, "\t%s\t%sL%d-", \ 2986 Pmode == DImode ? ".dword" : ".word", \ 2987 LOCAL_LABEL_PREFIX, VALUE); \ 2988 assemble_name (STREAM, XSTR (fnsym, 0)); \ 2989 fprintf (STREAM, "\n"); \ 2990 } \ 2991 else \ 2992 fprintf (STREAM, "\t%s\t%sL%d\n", \ 2993 ptr_mode == DImode ? ".dword" : ".word", \ 2994 LOCAL_LABEL_PREFIX, VALUE); \ 2995 } while (0) 2996 2997 /* Mark inline jump tables as data for the purpose of disassembly. For 2998 simplicity embed the jump table's label number in the local symbol 2999 produced so that multiple jump tables within a single function end 3000 up marked with unique symbols. Retain the alignment setting from 3001 `elfos.h' as we are replacing the definition from there. */ 3002 3003 #undef ASM_OUTPUT_BEFORE_CASE_LABEL 3004 #define ASM_OUTPUT_BEFORE_CASE_LABEL(STREAM, PREFIX, NUM, TABLE) \ 3005 do \ 3006 { \ 3007 ASM_OUTPUT_ALIGN ((STREAM), 2); \ 3008 if (JUMP_TABLES_IN_TEXT_SECTION) \ 3009 mips_set_text_contents_type (STREAM, "__jump_", NUM, FALSE); \ 3010 } \ 3011 while (0) 3012 3013 /* Reset text marking to code after an inline jump table. Like with 3014 the beginning of a jump table use the label number to keep symbols 3015 unique. */ 3016 3017 #define ASM_OUTPUT_CASE_END(STREAM, NUM, TABLE) \ 3018 do \ 3019 if (JUMP_TABLES_IN_TEXT_SECTION) \ 3020 mips_set_text_contents_type (STREAM, "__jend_", NUM, TRUE); \ 3021 while (0) 3022 3023 /* This is how to output an assembler line 3024 that says to advance the location counter 3025 to a multiple of 2**LOG bytes. */ 3026 3027 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \ 3028 fprintf (STREAM, "\t.align\t%d\n", (LOG)) 3029 3030 /* This is how to output an assembler line to advance the location 3031 counter by SIZE bytes. */ 3032 3033 #undef ASM_OUTPUT_SKIP 3034 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \ 3035 fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 3036 3037 /* This is how to output a string. */ 3038 #undef ASM_OUTPUT_ASCII 3039 #define ASM_OUTPUT_ASCII mips_output_ascii 3040 3041 3042 /* Default to -G 8 */ 3043 #ifndef MIPS_DEFAULT_GVALUE 3044 #define MIPS_DEFAULT_GVALUE 8 3045 #endif 3046 3047 /* Define the strings to put out for each section in the object file. */ 3048 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ 3049 #define DATA_SECTION_ASM_OP "\t.data" /* large data */ 3050 3051 #undef READONLY_DATA_SECTION_ASM_OP 3052 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */ 3053 3054 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ 3055 do \ 3056 { \ 3057 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \ 3058 TARGET_64BIT ? "daddiu" : "addiu", \ 3059 reg_names[STACK_POINTER_REGNUM], \ 3060 reg_names[STACK_POINTER_REGNUM], \ 3061 TARGET_64BIT ? "sd" : "sw", \ 3062 reg_names[REGNO], \ 3063 reg_names[STACK_POINTER_REGNUM]); \ 3064 } \ 3065 while (0) 3066 3067 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ 3068 do \ 3069 { \ 3070 mips_push_asm_switch (&mips_noreorder); \ 3071 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \ 3072 TARGET_64BIT ? "ld" : "lw", \ 3073 reg_names[REGNO], \ 3074 reg_names[STACK_POINTER_REGNUM], \ 3075 TARGET_64BIT ? "daddu" : "addu", \ 3076 reg_names[STACK_POINTER_REGNUM], \ 3077 reg_names[STACK_POINTER_REGNUM]); \ 3078 mips_pop_asm_switch (&mips_noreorder); \ 3079 } \ 3080 while (0) 3081 3082 /* How to start an assembler comment. 3083 The leading space is important (the mips native assembler requires it). */ 3084 #ifndef ASM_COMMENT_START 3085 #define ASM_COMMENT_START " #" 3086 #endif 3087 3088 #undef SIZE_TYPE 3089 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") 3090 3091 #undef PTRDIFF_TYPE 3092 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int") 3093 3094 /* The minimum alignment of any expanded block move. */ 3095 #define MIPS_MIN_MOVE_MEM_ALIGN 16 3096 3097 /* The maximum number of bytes that can be copied by one iteration of 3098 a cpymemsi loop; see mips_block_move_loop. */ 3099 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \ 3100 (UNITS_PER_WORD * 4) 3101 3102 /* The maximum number of bytes that can be copied by a straight-line 3103 implementation of cpymemsi; see mips_block_move_straight. We want 3104 to make sure that any loop-based implementation will iterate at 3105 least twice. */ 3106 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \ 3107 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2) 3108 3109 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These 3110 values were determined experimentally by benchmarking with CSiBE. 3111 In theory, the call overhead is higher for TARGET_ABICALLS (especially 3112 for o32 where we have to restore $gp afterwards as well as make an 3113 indirect call), but in practice, bumping this up higher for 3114 TARGET_ABICALLS doesn't make much difference to code size. */ 3115 3116 #define MIPS_CALL_RATIO 8 3117 3118 /* Any loop-based implementation of cpymemsi will have at least 3119 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory 3120 moves, so allow individual copies of fewer elements. 3121 3122 When cpymemsi is not available, use a value approximating 3123 the length of a memcpy call sequence, so that move_by_pieces 3124 will generate inline code if it is shorter than a function call. 3125 Since move_by_pieces_ninsns counts memory-to-memory moves, but 3126 we'll have to generate a load/store pair for each, halve the 3127 value of MIPS_CALL_RATIO to take that into account. */ 3128 3129 #define MOVE_RATIO(speed) \ 3130 (HAVE_cpymemsi \ 3131 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \ 3132 : MIPS_CALL_RATIO / 2) 3133 3134 /* For CLEAR_RATIO, when optimizing for size, give a better estimate 3135 of the length of a memset call, but use the default otherwise. */ 3136 3137 #define CLEAR_RATIO(speed)\ 3138 ((speed) ? 15 : MIPS_CALL_RATIO) 3139 3140 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when 3141 optimizing for size adjust the ratio to account for the overhead of 3142 loading the constant and replicating it across the word. */ 3143 3144 #define SET_RATIO(speed) \ 3145 ((speed) ? 15 : MIPS_CALL_RATIO - 2) 3146 3147 /* Since the bits of the _init and _fini function is spread across 3148 many object files, each potentially with its own GP, we must assume 3149 we need to load our GP. We don't preserve $gp or $ra, since each 3150 init/fini chunk is supposed to initialize $gp, and crti/crtn 3151 already take care of preserving $ra and, when appropriate, $gp. */ 3152 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32) 3153 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 3154 asm (SECTION_OP "\n\ 3155 .set push\n\ 3156 .set nomips16\n\ 3157 .set noreorder\n\ 3158 bal 1f\n\ 3159 nop\n\ 3160 1: .cpload $31\n\ 3161 .set reorder\n\ 3162 la $25, " USER_LABEL_PREFIX #FUNC "\n\ 3163 jalr $25\n\ 3164 .set pop\n\ 3165 " TEXT_SECTION_ASM_OP); 3166 #elif (defined _ABIN32 && _MIPS_SIM == _ABIN32) 3167 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 3168 asm (SECTION_OP "\n\ 3169 .set push\n\ 3170 .set nomips16\n\ 3171 .set noreorder\n\ 3172 bal 1f\n\ 3173 nop\n\ 3174 1: .set reorder\n\ 3175 .cpsetup $31, $2, 1b\n\ 3176 la $25, " USER_LABEL_PREFIX #FUNC "\n\ 3177 jalr $25\n\ 3178 .set pop\n\ 3179 " TEXT_SECTION_ASM_OP); 3180 #elif (defined _ABI64 && _MIPS_SIM == _ABI64) 3181 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 3182 asm (SECTION_OP "\n\ 3183 .set push\n\ 3184 .set nomips16\n\ 3185 .set noreorder\n\ 3186 bal 1f\n\ 3187 nop\n\ 3188 1: .set reorder\n\ 3189 .cpsetup $31, $2, 1b\n\ 3190 dla $25, " USER_LABEL_PREFIX #FUNC "\n\ 3191 jalr $25\n\ 3192 .set pop\n\ 3193 " TEXT_SECTION_ASM_OP); 3194 #endif 3195 3196 #ifndef HAVE_AS_TLS 3197 #define HAVE_AS_TLS 0 3198 #endif 3199 3200 #ifndef HAVE_AS_NAN 3201 #define HAVE_AS_NAN 0 3202 #endif 3203 3204 #ifndef USED_FOR_TARGET 3205 /* Information about ".set noFOO; ...; .set FOO" blocks. */ 3206 struct mips_asm_switch { 3207 /* The FOO in the description above. */ 3208 const char *name; 3209 3210 /* The current block nesting level, or 0 if we aren't in a block. */ 3211 int nesting_level; 3212 }; 3213 3214 extern const enum reg_class mips_regno_to_class[]; 3215 extern const char *current_function_file; /* filename current function is in */ 3216 extern int num_source_filenames; /* current .file # */ 3217 extern struct mips_asm_switch mips_noreorder; 3218 extern struct mips_asm_switch mips_nomacro; 3219 extern struct mips_asm_switch mips_noat; 3220 extern int mips_dbx_regno[]; 3221 extern int mips_dwarf_regno[]; 3222 extern bool mips_split_p[]; 3223 extern bool mips_split_hi_p[]; 3224 extern bool mips_use_pcrel_pool_p[]; 3225 extern const char *mips_lo_relocs[]; 3226 extern const char *mips_hi_relocs[]; 3227 extern enum processor mips_arch; /* which cpu to codegen for */ 3228 extern enum processor mips_tune; /* which cpu to schedule for */ 3229 extern int mips_isa; /* architectural level */ 3230 extern int mips_isa_rev; 3231 extern const struct mips_cpu_info *mips_arch_info; 3232 extern const struct mips_cpu_info *mips_tune_info; 3233 extern unsigned int mips_base_compression_flags; 3234 extern GTY(()) struct target_globals *mips16_globals; 3235 extern GTY(()) struct target_globals *micromips_globals; 3236 3237 /* Information about a function's frame layout. */ 3238 struct GTY(()) mips_frame_info { 3239 /* The size of the frame in bytes. */ 3240 HOST_WIDE_INT total_size; 3241 3242 /* The number of bytes allocated to variables. */ 3243 HOST_WIDE_INT var_size; 3244 3245 /* The number of bytes allocated to outgoing function arguments. */ 3246 HOST_WIDE_INT args_size; 3247 3248 /* The number of bytes allocated to the .cprestore slot, or 0 if there 3249 is no such slot. */ 3250 HOST_WIDE_INT cprestore_size; 3251 3252 /* Bit X is set if the function saves or restores GPR X. */ 3253 unsigned int mask; 3254 3255 /* Likewise FPR X. */ 3256 unsigned int fmask; 3257 3258 /* Likewise doubleword accumulator X ($acX). */ 3259 unsigned int acc_mask; 3260 3261 /* The number of GPRs, FPRs, doubleword accumulators and COP0 3262 registers saved. */ 3263 unsigned int num_gp; 3264 unsigned int num_fp; 3265 unsigned int num_acc; 3266 unsigned int num_cop0_regs; 3267 3268 /* The offset of the topmost GPR, FPR, accumulator and COP0-register 3269 save slots from the top of the frame, or zero if no such slots are 3270 needed. */ 3271 HOST_WIDE_INT gp_save_offset; 3272 HOST_WIDE_INT fp_save_offset; 3273 HOST_WIDE_INT acc_save_offset; 3274 HOST_WIDE_INT cop0_save_offset; 3275 3276 /* Likewise, but giving offsets from the bottom of the frame. */ 3277 HOST_WIDE_INT gp_sp_offset; 3278 HOST_WIDE_INT fp_sp_offset; 3279 HOST_WIDE_INT acc_sp_offset; 3280 HOST_WIDE_INT cop0_sp_offset; 3281 3282 /* Similar, but the value passed to _mcount. */ 3283 HOST_WIDE_INT ra_fp_offset; 3284 3285 /* The offset of arg_pointer_rtx from the bottom of the frame. */ 3286 HOST_WIDE_INT arg_pointer_offset; 3287 3288 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */ 3289 HOST_WIDE_INT hard_frame_pointer_offset; 3290 }; 3291 3292 /* Enumeration for masked vectored (VI) and non-masked (EIC) interrupts. */ 3293 enum mips_int_mask 3294 { 3295 INT_MASK_EIC = -1, 3296 INT_MASK_SW0 = 0, 3297 INT_MASK_SW1 = 1, 3298 INT_MASK_HW0 = 2, 3299 INT_MASK_HW1 = 3, 3300 INT_MASK_HW2 = 4, 3301 INT_MASK_HW3 = 5, 3302 INT_MASK_HW4 = 6, 3303 INT_MASK_HW5 = 7 3304 }; 3305 3306 /* Enumeration to mark the existence of the shadow register set. 3307 SHADOW_SET_INTSTACK indicates a shadow register set with a valid stack 3308 pointer. */ 3309 enum mips_shadow_set 3310 { 3311 SHADOW_SET_NO, 3312 SHADOW_SET_YES, 3313 SHADOW_SET_INTSTACK 3314 }; 3315 3316 struct GTY(()) machine_function { 3317 /* The next floating-point condition-code register to allocate 3318 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */ 3319 unsigned int next_fcc; 3320 3321 /* The register returned by mips16_gp_pseudo_reg; see there for details. */ 3322 rtx mips16_gp_pseudo_rtx; 3323 3324 /* The number of extra stack bytes taken up by register varargs. 3325 This area is allocated by the callee at the very top of the frame. */ 3326 int varargs_size; 3327 3328 /* The current frame information, calculated by mips_compute_frame_info. */ 3329 struct mips_frame_info frame; 3330 3331 /* The register to use as the function's global pointer, or INVALID_REGNUM 3332 if the function doesn't need one. */ 3333 unsigned int global_pointer; 3334 3335 /* How many instructions it takes to load a label into $AT, or 0 if 3336 this property hasn't yet been calculated. */ 3337 unsigned int load_label_num_insns; 3338 3339 /* True if mips_adjust_insn_length should ignore an instruction's 3340 hazard attribute. */ 3341 bool ignore_hazard_length_p; 3342 3343 /* True if the whole function is suitable for .set noreorder and 3344 .set nomacro. */ 3345 bool all_noreorder_p; 3346 3347 /* True if the function has "inflexible" and "flexible" references 3348 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p 3349 and mips_cfun_has_flexible_gp_ref_p for details. */ 3350 bool has_inflexible_gp_insn_p; 3351 bool has_flexible_gp_insn_p; 3352 3353 /* True if the function's prologue must load the global pointer 3354 value into pic_offset_table_rtx and store the same value in 3355 the function's cprestore slot (if any). Even if this value 3356 is currently false, we may decide to set it to true later; 3357 see mips_must_initialize_gp_p () for details. */ 3358 bool must_initialize_gp_p; 3359 3360 /* True if the current function must restore $gp after any potential 3361 clobber. This value is only meaningful during the first post-epilogue 3362 split_insns pass; see mips_must_initialize_gp_p () for details. */ 3363 bool must_restore_gp_when_clobbered_p; 3364 3365 /* True if this is an interrupt handler. */ 3366 bool interrupt_handler_p; 3367 3368 /* Records the way in which interrupts should be masked. Only used if 3369 interrupts are not kept masked. */ 3370 enum mips_int_mask int_mask; 3371 3372 /* Records if this is an interrupt handler that uses shadow registers. */ 3373 enum mips_shadow_set use_shadow_register_set; 3374 3375 /* True if this is an interrupt handler that should keep interrupts 3376 masked. */ 3377 bool keep_interrupts_masked_p; 3378 3379 /* True if this is an interrupt handler that should use DERET 3380 instead of ERET. */ 3381 bool use_debug_exception_return_p; 3382 3383 /* True if at least one of the formal parameters to a function must be 3384 written to the frame header (probably so its address can be taken). */ 3385 bool does_not_use_frame_header; 3386 3387 /* True if none of the functions that are called by this function need 3388 stack space allocated for their arguments. */ 3389 bool optimize_call_stack; 3390 3391 /* True if one of the functions calling this function may not allocate 3392 a frame header. */ 3393 bool callers_may_not_allocate_frame; 3394 3395 /* True if GCC stored callee saved registers in the frame header. */ 3396 bool use_frame_header_for_callee_saved_regs; 3397 }; 3398 #endif 3399 3400 /* Enable querying of DFA units. */ 3401 #define CPU_UNITS_QUERY 1 3402 3403 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 3404 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS) 3405 3406 /* As on most targets, we want the .eh_frame section to be read-only where 3407 possible. And as on most targets, this means two things: 3408 3409 (a) Non-locally-binding pointers must have an indirect encoding, 3410 so that the addresses in the .eh_frame section itself become 3411 locally-binding. 3412 3413 (b) A shared library's .eh_frame section must encode locally-binding 3414 pointers in a relative (relocation-free) form. 3415 3416 However, MIPS has traditionally not allowed directives like: 3417 3418 .long x-. 3419 3420 in cases where "x" is in a different section, or is not defined in the 3421 same assembly file. We are therefore unable to emit the PC-relative 3422 form required by (b) at assembly time. 3423 3424 Fortunately, the linker is able to convert absolute addresses into 3425 PC-relative addresses on our behalf. Unfortunately, only certain 3426 versions of the linker know how to do this for indirect pointers, 3427 and for personality data. We must fall back on using writable 3428 .eh_frame sections for shared libraries if the linker does not 3429 support this feature. */ 3430 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 3431 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr) 3432 3433 /* For switching between MIPS16 and non-MIPS16 modes. */ 3434 #define SWITCHABLE_TARGET 1 3435 3436 /* Several named MIPS patterns depend on Pmode. These patterns have the 3437 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode. 3438 Add the appropriate suffix to generator function NAME and invoke it 3439 with arguments ARGS. */ 3440 #define PMODE_INSN(NAME, ARGS) \ 3441 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS) 3442 3443 /* If we are *not* using multilibs and the default ABI is not ABI_32 we 3444 need to change these from /lib and /usr/lib. */ 3445 #if MIPS_ABI_DEFAULT == ABI_N32 3446 #define STANDARD_STARTFILE_PREFIX_1 "/lib32/" 3447 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/" 3448 #elif MIPS_ABI_DEFAULT == ABI_64 3449 #define STANDARD_STARTFILE_PREFIX_1 "/lib64/" 3450 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/" 3451 #endif 3452 3453 /* Load store bonding is not supported by micromips and fix_24k. The 3454 performance can be degraded for those targets. Hence, do not bond for 3455 micromips or fix_24k. */ 3456 #define ENABLE_LD_ST_PAIRS \ 3457 (TARGET_LOAD_STORE_PAIRS \ 3458 && (TUNE_P5600 || TUNE_I6400 || TUNE_P6600) \ 3459 && !TARGET_MICROMIPS && !TARGET_FIX_24K) 3460 3461 #define NEED_INDICATE_EXEC_STACK 0 3462 3463 /* Define the shadow offset for asan. Other OS's can override in the 3464 respective tm.h files. */ 3465 #ifndef SUBTARGET_SHADOW_OFFSET 3466 #define SUBTARGET_SHADOW_OFFSET \ 3467 (POINTER_SIZE == 64 ? HOST_WIDE_INT_1 << 37 : HOST_WIDE_INT_C (0x0aaa0000)) 3468 #endif 3469