xref: /netbsd-src/sys/arch/mips/cavium/dev/octeon_twsireg.h (revision 13d5e9b5fa08db7d5b049affd78f108a76f66704)
1 /*	$NetBSD: octeon_twsireg.h,v 1.3 2020/06/22 03:05:07 simonb Exp $	*/
2 
3 /*
4  * Copyright (c) 2007 Internet Initiative Japan, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 /*
30  * TWSI Registers
31  */
32 
33 #ifndef _OCTEON_TWSIREG_H_
34 #define _OCTEON_TWSIREG_H_
35 
36 /* ---- register addresses */
37 
38 #define	MIO_TWS_SW_TWSI				0x0001180000001000ULL
39 #define	MIO_TWS_TWSI_SW				0x0001180000001008ULL
40 #define	MIO_TWS_INT				0x0001180000001010ULL
41 #define	MIO_TWS_SW_TWSI_EXT			0x0001180000001018ULL
42 
43 /* ---- register bits */
44 
45 #define	MIO_TWS_SW_TWSI_V			UINT64_C(0x8000000000000000)
46 #define	MIO_TWS_SW_TWSI_SLONLY			UINT64_C(0x4000000000000000)
47 #define	MIO_TWS_SW_TWSI_EIA			UINT64_C(0x2000000000000000)
48 #define	MIO_TWS_SW_TWSI_OP			UINT64_C(0x1e00000000000000)
49 #define	  MIO_TWS_SW_TWSI_OP_ONE		  0
50 #define	  MIO_TWS_SW_TWSI_OP_MCLK		  4
51 #define	  MIO_TWS_SW_TWSI_OP_EXTEND		  6
52 #define	  MIO_TWS_SW_TWSI_OP_FOUR		  8
53 #define	  MIO_TWS_SW_TWSI_OP_COMBR		  1
54 #define	  MIO_TWS_SW_TWSI_OP_10BIT		  2
55 #define	MIO_TWS_SW_TWSI_R			UINT64_C(0x0100000000000000)
56 #define	MIO_TWS_SW_TWSI_SOVR			UINT64_C(0x0080000000000000)
57 #define	MIO_TWS_SW_TWSI_SIZE			UINT64_C(0x0070000000000000)
58 #define	MIO_TWS_SW_TWSI_SCR			UINT64_C(0x000c000000000000)
59 #define	MIO_TWS_SW_TWSI_A			UINT64_C(0x0003ff0000000000)
60 #define	MIO_TWS_SW_TWSI_IA			UINT64_C(0x000000f800000000)
61 #define	MIO_TWS_SW_TWSI_EOP_IA			UINT64_C(0x0000000700000000)
62 #define	  MIO_TWS_SW_TWSI_EOP_IA_TWSI_SLAVE_ADD	  0
63 #define	  MIO_TWS_SW_TWSI_EOP_IA_TWSI_DATA	  1
64 #define	  MIO_TWS_SW_TWSI_EOP_IA_TWSI_CTL	  2
65 #define	  MIO_TWS_SW_TWSI_EOP_IA_TWSI_CLKCTL	  3
66 #define	  MIO_TWS_SW_TWSI_EOP_IA_TWSI_STAT	  3
67 #define	  MIO_TWS_SW_TWSI_EOP_IA_TWSI_SLAVE_ADD_EXT 4
68 #define	  MIO_TWS_SW_TWSI_EOP_IA_TWSI_RST	  7
69 #define	MIO_TWS_SW_TWSI_D			UINT64_C(0x00000000ffffffff)
70 
71 #define	MIO_TWS_TWSI_SW_V			UINT64_C(0xc000000000000000)
72 #define	MIO_TWS_TWSI_SW_XXX_61_32		UINT64_C(0x3fffffff00000000)
73 #define	MIO_TWS_TWSI_SW_D			UINT64_C(0x00000000ffffffff)
74 
75 #define	MIO_TWS_INT_XXX_63_12			UINT64_C(0xfffffffffffff000)
76 #define	MIO_TWS_INT_SCL				UINT64_C(0x0000000000000800)
77 #define	MIO_TWS_INT_SDA				UINT64_C(0x0000000000000400)
78 #define	MIO_TWS_INT_SCL_OVR			UINT64_C(0x0000000000000200)
79 #define	MIO_TWS_INT_SDA_OVR			UINT64_C(0x0000000000000100)
80 #define	MIO_TWS_INT_XXX_7			UINT64_C(0x0000000000000080)
81 #define	MIO_TWS_INT_CORE_EN			UINT64_C(0x0000000000000040)
82 #define	MIO_TWS_INT_TS_EN			UINT64_C(0x0000000000000020)
83 #define	MIO_TWS_INT_ST_EN			UINT64_C(0x0000000000000010)
84 #define	MIO_TWS_INT_XXX_3			UINT64_C(0x0000000000000008)
85 #define	MIO_TWS_INT_CORE_INT			UINT64_C(0x0000000000000004)
86 #define	MIO_TWS_INT_TS_INT			UINT64_C(0x0000000000000002)
87 #define	MIO_TWS_INT_ST_INT			UINT64_C(0x0000000000000001)
88 
89 #define	MIO_TWS_SW_TWSI_EXT_XXX_63_40		UINT64_C(0xffffff0000000000)
90 #define	MIO_TWS_SW_TWSI_EXT_IA			UINT64_C(0x000000ff00000000)
91 #define	MIO_TWS_SW_TWSI_EXT_D			UINT64_C(0x00000000ffffffff)
92 
93 /*
94  * TWSI Control Registers
95  */
96 
97 /* TWSI Slave Address Registers */
98 
99 #define	TWSI_SLAVE_ADD_ADDR			0xfe
100 #define	TWSI_SLAVE_ADD_GCE			UINT8_C(0x01)
101 
102 /* TWSI Slave Extended-Address Registers */
103 
104 /* TWSI Data Register */
105 
106 /* TWSI Control Register */
107 
108 #define	TWSI_CTL_CE				UINT8_C(0x80)
109 #define	TWSI_CTL_ENAB				UINT8_C(0x40)
110 #define	TWSI_CTL_STA				UINT8_C(0x20)
111 #define	TWSI_CTL_STP				UINT8_C(0x10)
112 #define	TWSI_CTL_IFLG				UINT8_C(0x08)
113 #define	TWSI_CTL_AAK				UINT8_C(0x04)
114 #define	TWSI_CTL_XXX_1_0			0x03
115 
116 /* ---- bus_space */
117 
118 #define	MIO_TWS_NUNITS				1
119 #define	MIO_TWS_BASE_0				0x0001180000001000ULL
120 #define	MIO_TWS_SIZE				0x0020
121 
122 #define	MIO_TWS_SW_TWSI_OFFSET			0x0000
123 #define	MIO_TWS_TWSI_SW_OFFSET			0x0008
124 #define	MIO_TWS_INT_OFFSET			0x0010
125 #define	MIO_TWS_SW_TWSI_EXT_OFFSET		0x0018
126 
127 #endif /* _OCTEON_TWSIREG_H_ */
128