| /llvm-project/llvm/unittests/Target/RISCV/ |
| H A D | RISCVInstrInfoTest.cpp | 74 MachineInstr *MI1 = BuildMI(*MF, DL, TII->get(RISCV::ADDI), RISCV::X1) in TEST_P() local
104 MachineInstr *MI1 = BuildMI(*MF, DL, TII->get(RISCV::ADDI), RISCV::X1) in TEST_P() local
258 auto *MI1 = BuildMI(*MBB, MBB->begin(), DL, TII->get(RISCV::ADDI), RISCV::X1) TEST_P() local
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| /llvm-project/llvm/unittests/CodeGen/ |
| H A D | MachineBasicBlockTest.cpp | 77 MBB.insert(MBB.begin(), MI1); in TEST() local
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| H A D | MachineInstrTest.cpp | 69 auto MI1 = MF->CreateMachineInstr(Table.MCID, DebugLoc()); in TEST() local
107 void checkHashAndIsEqualMatch(MachineInstr *MI1, MachineInstr *MI2) { in checkHashAndIsEqualMatch() argument
[all...] |
| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64MachineScheduler.cpp | 36 static bool mayOverlapWrite(const MachineInstr &MI0, const MachineInstr &MI1, in mayOverlapWrite()
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| H A D | AArch64CollectLOH.cpp | 281 const MachineInstr *MI1; ///< Second instruction involved in the LOH global() member
[all...] |
| /llvm-project/llvm/lib/CodeGen/ |
| H A D | DFAPacketizer.cpp | 272 bool VLIWPacketizerList::alias(const MachineInstr &MI1, in alias()
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| H A D | TargetInstrInfo.cpp | 429 const MachineInstr &MI1, in produceSameValue() argument
841 MachineInstr *MI1 = nullptr; hasReassociableOperands() local
861 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); hasReassociableSibling() local
[all...] |
| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsSizeReduction.cpp | 398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr()
464 MachineInstr *MI1 = Arguments->MI; in ReduceXWtoXWP() local
621 MachineInstr *MI1 = Arguments->MI; in ReduceMoveToMovep() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86OptimizeLEAs.cpp | 397 int64_t X86OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, in getAddrDispShift() argument
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 1825 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); hasReassociableVectorSibling() local
1854 MachineInstr *MI1 = nullptr; hasReassociableOperands() local
2647 memOpsHaveSameBasePtr(const MachineInstr & MI1,ArrayRef<const MachineOperand * > BaseOps1,const MachineInstr & MI2,ArrayRef<const MachineOperand * > BaseOps2) memOpsHaveSameBasePtr() argument
3863 hasEqualFRM(const MachineInstr & MI1,const MachineInstr & MI2) hasEqualFRM() argument
[all...] |
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 264 MachineInstr &MI1 = *SU.getInstr(); apply() local
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| H A D | HexagonVLIWPacketizer.cpp | 967 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, in arePredicatesComplements() argument
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| H A D | HexagonInstrInfo.cpp | 2687 isToBeScheduledASAP(const MachineInstr & MI1,const MachineInstr & MI2) const isToBeScheduledASAP() argument
3063 addLatencyToSchedule(const MachineInstr & MI1,const MachineInstr & MI2) const addLatencyToSchedule() argument
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LoadStoreOpt.cpp | 104 aliasIsKnownForLoadStore(const MachineInstr & MI1,const MachineInstr & MI2,bool & IsAlias,MachineRegisterInfo & MRI) aliasIsKnownForLoadStore() argument
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| H A D | CombinerHelper.cpp | 5627 hasMoreUses(const MachineInstr & MI0,const MachineInstr & MI1,const MachineRegisterInfo & MRI) hasMoreUses() argument
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| /llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRExpandPseudoInsts.cpp | 1646 auto MI1 = in expandLSLW4Rd() local
1732 auto MI1 = in expandLSLW12Rd() local
1844 auto MI1 = in expandLSRW4Rd() local
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| /llvm-project/clang-tools-extra/test/clang-tidy/checkers/bugprone/ |
| H A D | easily-swappable-parameters-len2.cpp | 148 void typedefChain(int I, MyInt1 MI1, MyInt2 MI2, MyInt2b MI2b) {} in typedefChain()
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 472 MachineInstr *MI1 = *I1; hoistAndMergeSGPRInits() local
[all...] |
| H A D | GCNHazardRecognizer.cpp | 2223 const MachineInstr *MI1; checkMAIHazards90A() local
[all...] |
| H A D | SIInstrInfo.cpp | 519 memOpsHaveSameBasePtr(const MachineInstr & MI1,ArrayRef<const MachineOperand * > BaseOps1,const MachineInstr & MI2,ArrayRef<const MachineOperand * > BaseOps2) memOpsHaveSameBasePtr() argument
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 1862 produceSameValue(const MachineInstr & MI0,const MachineInstr & MI1,const MachineRegisterInfo * MRI) const produceSameValue() argument
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