1 /* $OpenBSD: gcu_reg.h,v 1.1 2009/11/25 13:28:13 dms Exp $ */ 2 3 /* 4 * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * version: Embedded.B.1.0.3-146 34 */ 35 36 /* 37 * gcu_reg.h 38 * Macros and constants related to the registers available on the GCU 39 */ 40 41 #ifndef GCU_REG_H 42 #define GCU_REG_H 43 44 /* Register Offsets within memory map register space */ 45 #define MDIO_STATUS_REG 0x00000010UL 46 #define MDIO_COMMAND_REG 0x00000014UL 47 48 /* MDIO_STATUS_REG fields */ 49 #define MDIO_STATUS_STATUS_MASK 0x80000000UL /* bit 31 = 1 on error */ 50 #define MDIO_STATUS_READ_DATA_MASK 0x0000FFFFUL 51 52 /* MDIO_COMMAND_REG fields */ 53 #define MDIO_COMMAND_GO_MASK 0x80000000UL /* bit 31 = 1 during read or 54 * write, 0 on completion */ 55 #define MDIO_COMMAND_OPER_MASK 0x04000000UL /* bit = 1 is a write */ 56 #define MDIO_COMMAND_PHY_ADDR_MASK 0x03E00000UL 57 #define MDIO_COMMAND_PHY_REG_MASK 0x001F0000UL 58 #define MDIO_COMMAND_WRITE_DATA_MASK 0x0000FFFFUL 59 60 #define MDIO_COMMAND_GO_OFFSET 31 61 #define MDIO_COMMAND_OPER_OFFSET 26 62 #define MDIO_COMMAND_PHY_ADDR_OFFSET 21 63 #define MDIO_COMMAND_PHY_REG_OFFSET 16 64 #define MDIO_COMMAND_WRITE_DATA_OFFSET 0 65 66 #define MDIO_COMMAND_PHY_ADDR_MAX 2 /* total phys supported by GCU */ 67 #define MDIO_COMMAND_PHY_REG_MAX 31 /* total registers available on 68 * the M88 Phy used on truxton */ 69 70 #endif /* ifndef GCU_REG_H */ 71 72