1 /* $NetBSD: tegra_mcreg.h,v 1.3 2017/01/22 17:43:23 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_TEGRA_MCREG_H 30 #define _ARM_TEGRA_MCREG_H 31 32 #define MC_INTSTATUS_REG 0x00 33 #define MC_INTMASK_REG 0x04 34 35 #define MC_INT_DECERR_MTS __BIT(16) 36 #define MC_INT_SECERR_SEC __BIT(13) 37 #define MC_INT_DECERR_VPR __BIT(12) 38 #define MC_INT_INVALID_APB_ASID_UPDATE __BIT(11) 39 #define MC_INT_INVALID_SMMU_PAGE __BIT(10) 40 #define MC_INT_SECURITY_VIOLATION __BIT(8) 41 #define MC_INT_ARBITRATION_EMEM __BIT(9) 42 #define MC_INT_DECERR_EMEM __BIT(6) 43 #define MC_INT__ALL (MC_INT_DECERR_MTS | \ 44 MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | \ 45 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE | \ 46 MC_INT_SECURITY_VIOLATION | MC_INT_ARBITRATION_EMEM | \ 47 MC_INT_DECERR_EMEM) 48 49 #define MC_ERR_STATUS_REG 0x08 50 51 #define MC_ERR_TYPE __BITS(30,28) 52 #define MC_ERR_INVALID_SMMU_PAGE_READABLE __BIT(27) 53 #define MC_ERR_INVALID_SMMU_PAGE_WRITABLE __BIT(26) 54 #define MC_ERR_INVALID_SMMU_PAGE_NONSECURE __BIT(25) 55 #define MC_ERR_ADDR_HI __BITS(21,20) 56 #define MC_ERR_SWAP __BIT(18) 57 #define MC_ERR_SECURITY __BIT(17) 58 #define MC_ERR_RW __BIT(16) 59 #define MC_ERR_RW_READ 0 60 #define MC_ERR_RW_WRITE 1 61 #define MC_ERR_ADR1 __BITS(14,12) 62 #define MC_ERR_ID __BITS(6,0) 63 64 #define MC_ERR_ADR_REG 0x0c 65 66 #define MC_SMMU_CONFIG_REG 0x10 67 #define MC_SMMU_ENABLE __BIT(0) 68 69 #define MC_SMMU_TLB_CONFIG_REG 0x14 70 #define MC_SMMU_PTC_CONFIG_REG 0x18 71 #define MC_SMMU_PTB_ASID_REG 0x1c 72 #define MC_SMMU_PTB_DATA_REG 0x20 73 #define MC_SMMU_TLB_FLUSH_REG 0x30 74 #define MC_SMMU_PTC_FLUSH_REG 0x34 75 76 #define MC_EMEM_CFG_0_REG 0x50 77 78 #define MC_EMEM_CFG_0_EMEM_BOM __BIT(31) 79 #define MC_EMEM_CFG_0_EMEM_SIZE_MB __BITS(13,0) 80 81 #define MC_SMMU_TRANSLATION_ENABLE_0_REG 0x228 82 #define MC_SMMU_AFIR_ENABLE __BIT(14) 83 #define MC_SMMU_TRANSLATION_ENABLE_1_REG 0x22c 84 #define MC_SMMU_AFIW_ENABLE __BIT(17) 85 #define MC_SMMU_TRANSLATION_ENABLE_2_REG 0x230 86 #define MC_SMMU_TRANSLATION_ENABLE_3_REG 0x234 87 #define MC_SMMU_AFI_ASID_REG 0x238 88 89 #endif /* _ARM_TEGRA_MCREG_H */ 90