xref: /openbsd-src/gnu/usr.bin/gcc/gcc/config/mips/mips.h (revision e97b50d07db9d2e38056ac70773ec1d6db82d1a7)
1 /* Definitions of target machine for GNU compiler.  MIPS version.
2    Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3    1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
4    Contributed by A. Lichnewsky (lich@inria.inria.fr).
5    Changed by Michael Meissner	(meissner@osf.org).
6    64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7    Brendan Eich (brendan@microunity.com).
8 
9 This file is part of GNU CC.
10 
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15 
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 GNU General Public License for more details.
20 
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING.  If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA.  */
25 
26 
27 /* Standard GCC variables that we reference.  */
28 
29 extern char    *asm_file_name;
30 extern char	call_used_regs[];
31 extern int	may_call_alloca;
32 extern char   **save_argv;
33 extern int	target_flags;
34 
35 /* MIPS external variables defined in mips.c.  */
36 
37 /* comparison type */
38 enum cmp_type {
39   CMP_SI,				/* compare four byte integers */
40   CMP_DI,				/* compare eight byte integers */
41   CMP_SF,				/* compare single precision floats */
42   CMP_DF,				/* compare double precision floats */
43   CMP_MAX				/* max comparison type */
44 };
45 
46 /* types of delay slot */
47 enum delay_type {
48   DELAY_NONE,				/* no delay slot */
49   DELAY_LOAD,				/* load from memory delay */
50   DELAY_HILO,				/* move from/to hi/lo registers */
51   DELAY_FCMP				/* delay after doing c.<xx>.{d,s} */
52 };
53 
54 /* Which processor to schedule for.  Since there is no difference between
55    a R2000 and R3000 in terms of the scheduler, we collapse them into
56    just an R3000.  The elements of the enumeration must match exactly
57    the cpu attribute in the mips.md machine description.  */
58 
59 enum processor_type {
60   PROCESSOR_DEFAULT,
61   PROCESSOR_R3000,
62   PROCESSOR_R3900,
63   PROCESSOR_R6000,
64   PROCESSOR_R4000,
65   PROCESSOR_R4100,
66   PROCESSOR_R4111,
67   PROCESSOR_R4120,
68   PROCESSOR_R4300,
69   PROCESSOR_R4600,
70   PROCESSOR_R4650,
71   PROCESSOR_R5000,
72   PROCESSOR_R5400,
73   PROCESSOR_R5500,
74   PROCESSOR_R8000,
75   PROCESSOR_R4KC,
76   PROCESSOR_R5KC,
77   PROCESSOR_R20KC,
78   PROCESSOR_SR71000,
79   PROCESSOR_SB1
80 };
81 
82 /* Recast the cpu class to be the cpu attribute.  */
83 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
84 
85 /* Which ABI to use.  ABI_32 (original 32, or o32), ABI_N32 (n32),
86    ABI_64 (n64) are all defined by SGI.  ABI_O64 is o32 extended
87    to work on a 64 bit machine.  */
88 
89 #define ABI_32  0
90 #define ABI_N32 1
91 #define ABI_64  2
92 #define ABI_EABI 3
93 #define ABI_O64  4
94 /* MEABI is gcc's internal name for MIPS' new EABI (defined by MIPS)
95    which is not the same as the above EABI (defined by Cygnus,
96    Greenhills, and Toshiba?).  MEABI is not yet complete or published,
97    but at this point it looks like N32 as far as calling conventions go,
98    but allows for either 32 or 64 bit registers.
99 
100    Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus'
101    EABI the legacy EABI.  In the end we may end up calling both ABI's
102    EABI but give them different version numbers, but for now I'm going
103    with different names.  */
104 #define ABI_MEABI 5
105 
106 /* Whether to emit abicalls code sequences or not.  */
107 
108 enum mips_abicalls_type {
109   MIPS_ABICALLS_NO,
110   MIPS_ABICALLS_YES
111 };
112 
113 /* Recast the abicalls class to be the abicalls attribute.  */
114 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
115 
116 /* Which type of block move to do (whether or not the last store is
117    split out so it can fill a branch delay slot).  */
118 
119 enum block_move_type {
120   BLOCK_MOVE_NORMAL,			/* generate complete block move */
121   BLOCK_MOVE_NOT_LAST,			/* generate all but last store */
122   BLOCK_MOVE_LAST			/* generate just the last store */
123 };
124 
125 /* Information about one recognized processor.  Defined here for the
126    benefit of TARGET_CPU_CPP_BUILTINS.  */
127 struct mips_cpu_info {
128   /* The 'canonical' name of the processor as far as GCC is concerned.
129      It's typically a manufacturer's prefix followed by a numerical
130      designation.  It should be lower case.  */
131   const char *name;
132 
133   /* The internal processor number that most closely matches this
134      entry.  Several processors can have the same value, if there's no
135      difference between them from GCC's point of view.  */
136   enum processor_type cpu;
137 
138   /* The ISA level that the processor implements.  */
139   int isa;
140 };
141 
142 extern char mips_reg_names[][8];	/* register names (a0 vs. $4).  */
143 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
144 extern const char *current_function_file; /* filename current function is in */
145 extern int num_source_filenames;	/* current .file # */
146 extern int inside_function;		/* != 0 if inside of a function */
147 extern int ignore_line_number;		/* != 0 if we are to ignore next .loc */
148 extern int file_in_function_warning;	/* warning given about .file in func */
149 extern int sdb_label_count;		/* block start/end next label # */
150 extern int sdb_begin_function_line;     /* Starting Line of current function */
151 extern int mips_section_threshold;	/* # bytes of data/sdata cutoff */
152 extern int g_switch_value;		/* value of the -G xx switch */
153 extern int g_switch_set;		/* whether -G xx was passed.  */
154 extern int sym_lineno;			/* sgi next label # for each stmt */
155 extern int set_noreorder;		/* # of nested .set noreorder's  */
156 extern int set_nomacro;			/* # of nested .set nomacro's  */
157 extern int set_noat;			/* # of nested .set noat's  */
158 extern int set_volatile;		/* # of nested .set volatile's  */
159 extern int mips_branch_likely;		/* emit 'l' after br (branch likely) */
160 extern int mips_dbx_regno[];		/* Map register # to debug register # */
161 extern GTY(()) rtx branch_cmp[2];	/* operands for compare */
162 extern enum cmp_type branch_type;	/* what type of branch to use */
163 extern enum processor_type mips_arch;   /* which cpu to codegen for */
164 extern enum processor_type mips_tune;   /* which cpu to schedule for */
165 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
166 extern int mips_isa;			/* architectural level */
167 extern int mips16;			/* whether generating mips16 code */
168 extern int mips16_hard_float;		/* mips16 without -msoft-float */
169 extern int mips_entry;			/* generate entry/exit for mips16 */
170 extern const char *mips_arch_string;    /* for -march=<xxx> */
171 extern const char *mips_tune_string;    /* for -mtune=<xxx> */
172 extern const char *mips_isa_string;	/* for -mips{1,2,3,4} */
173 extern const char *mips_abi_string;	/* for -mabi={32,n32,64} */
174 extern const char *mips_entry_string;	/* for -mentry */
175 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
176 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
177 extern int mips_split_addresses;	/* perform high/lo_sum support */
178 extern int dslots_load_total;		/* total # load related delay slots */
179 extern int dslots_load_filled;		/* # filled load delay slots */
180 extern int dslots_jump_total;		/* total # jump related delay slots */
181 extern int dslots_jump_filled;		/* # filled jump delay slots */
182 extern int dslots_number_nops;		/* # of nops needed by previous insn */
183 extern int num_refs[3];			/* # 1/2/3 word references */
184 extern GTY(()) rtx mips_load_reg;	/* register to check for load delay */
185 extern GTY(()) rtx mips_load_reg2;	/* 2nd reg to check for load delay */
186 extern GTY(()) rtx mips_load_reg3;	/* 3rd reg to check for load delay */
187 extern GTY(()) rtx mips_load_reg4;	/* 4th reg to check for load delay */
188 extern int mips_string_length;		/* length of strings for mips16 */
189 extern const struct mips_cpu_info mips_cpu_info_table[];
190 extern const struct mips_cpu_info *mips_arch_info;
191 extern const struct mips_cpu_info *mips_tune_info;
192 
193 /* Functions to change what output section we are using.  */
194 extern void		sdata_section PARAMS ((void));
195 extern void		sbss_section PARAMS ((void));
196 
197 /* Macros to silence warnings about numbers being signed in traditional
198    C and unsigned in ISO C when compiled on 32-bit hosts.  */
199 
200 #define BITMASK_HIGH	(((unsigned long)1) << 31)	/* 0x80000000 */
201 #define BITMASK_UPPER16	((unsigned long)0xffff << 16)	/* 0xffff0000 */
202 #define BITMASK_LOWER16	((unsigned long)0xffff)		/* 0x0000ffff */
203 
204 
205 /* Run-time compilation parameters selecting different hardware subsets.  */
206 
207 /* Macros used in the machine description to test the flags.  */
208 
209 					/* Bits for real switches */
210 #define MASK_INT64	   0x00000001	/* ints are 64 bits */
211 #define MASK_LONG64	   0x00000002	/* longs are 64 bits */
212 #define MASK_SPLIT_ADDR	   0x00000004	/* Address splitting is enabled.  */
213 #define MASK_GPOPT	   0x00000008	/* Optimize for global pointer */
214 #define MASK_GAS	   0x00000010	/* Gas used instead of MIPS as */
215 #define MASK_NAME_REGS	   0x00000020	/* Use MIPS s/w reg name convention */
216 #define MASK_STATS	   0x00000040	/* print statistics to stderr */
217 #define MASK_MEMCPY	   0x00000080	/* call memcpy instead of inline code*/
218 #define MASK_SOFT_FLOAT	   0x00000100	/* software floating point */
219 #define MASK_FLOAT64	   0x00000200	/* fp registers are 64 bits */
220 #define MASK_ABICALLS	   0x00000400	/* emit .abicalls/.cprestore/.cpload */
221 #define MASK_UNUSED1	   0x00000800	/* Unused Mask.  */
222 #define MASK_LONG_CALLS	   0x00001000	/* Always call through a register */
223 #define MASK_64BIT	   0x00002000	/* Use 64 bit GP registers and insns */
224 #define MASK_EMBEDDED_PIC  0x00004000	/* Generate embedded PIC code */
225 #define MASK_EMBEDDED_DATA 0x00008000	/* Reduce RAM usage, not fast code */
226 #define MASK_BIG_ENDIAN	   0x00010000	/* Generate big endian code */
227 #define MASK_SINGLE_FLOAT  0x00020000	/* Only single precision FPU.  */
228 #define MASK_MAD	   0x00040000	/* Generate mad/madu as on 4650.  */
229 #define MASK_4300_MUL_FIX  0x00080000   /* Work-around early Vr4300 CPU bug */
230 #define MASK_MIPS16	   0x00100000	/* Generate mips16 code */
231 #define MASK_NO_CHECK_ZERO_DIV \
232 			   0x00200000	/* divide by zero checking */
233 #define MASK_CHECK_RANGE_DIV \
234 			   0x00400000	/* divide result range checking */
235 #define MASK_UNINIT_CONST_IN_RODATA \
236 			   0x00800000	/* Store uninitialized
237 					   consts in rodata */
238 #define MASK_NO_FUSED_MADD 0x01000000   /* Don't generate floating point
239 					   multiply-add operations.  */
240 #define MASK_BRANCHLIKELY  0x02000000   /* Generate Branch Likely
241 					   instructions.  */
242 
243 					/* Debug switches, not documented */
244 #define MASK_DEBUG	0		/* unused */
245 #define MASK_DEBUG_A	0		/* don't allow <label>($reg) addrs */
246 #define MASK_DEBUG_B	0		/* GO_IF_LEGITIMATE_ADDRESS debug */
247 #define MASK_DEBUG_C	0		/* don't expand seq, etc.  */
248 #define MASK_DEBUG_D	0		/* don't do define_split's */
249 #define MASK_DEBUG_E	0		/* function_arg debug */
250 #define MASK_DEBUG_F	0		/* ??? */
251 #define MASK_DEBUG_G	0		/* don't support 64 bit arithmetic */
252 #define MASK_DEBUG_I	0		/* unused */
253 
254 					/* Dummy switches used only in specs */
255 #define MASK_MIPS_TFILE	0		/* flag for mips-tfile usage */
256 
257 					/* r4000 64 bit sizes */
258 #define TARGET_INT64		(target_flags & MASK_INT64)
259 #define TARGET_LONG64		(target_flags & MASK_LONG64)
260 #define TARGET_FLOAT64		(target_flags & MASK_FLOAT64)
261 #define TARGET_64BIT		(target_flags & MASK_64BIT)
262 
263 					/* Mips vs. GNU linker */
264 #define TARGET_SPLIT_ADDRESSES	(target_flags & MASK_SPLIT_ADDR)
265 
266 					/* Mips vs. GNU assembler */
267 #define TARGET_GAS		(target_flags & MASK_GAS)
268 #define TARGET_MIPS_AS		(!TARGET_GAS)
269 
270 					/* Debug Modes */
271 #define TARGET_DEBUG_MODE	(target_flags & MASK_DEBUG)
272 #define TARGET_DEBUG_A_MODE	(target_flags & MASK_DEBUG_A)
273 #define TARGET_DEBUG_B_MODE	(target_flags & MASK_DEBUG_B)
274 #define TARGET_DEBUG_C_MODE	(target_flags & MASK_DEBUG_C)
275 #define TARGET_DEBUG_D_MODE	(target_flags & MASK_DEBUG_D)
276 #define TARGET_DEBUG_E_MODE	(target_flags & MASK_DEBUG_E)
277 #define TARGET_DEBUG_F_MODE	(target_flags & MASK_DEBUG_F)
278 #define TARGET_DEBUG_G_MODE	(target_flags & MASK_DEBUG_G)
279 #define TARGET_DEBUG_I_MODE	(target_flags & MASK_DEBUG_I)
280 
281 					/* Reg. Naming in .s ($21 vs. $a0) */
282 #define TARGET_NAME_REGS	(target_flags & MASK_NAME_REGS)
283 
284 					/* Optimize for Sdata/Sbss */
285 #define TARGET_GP_OPT		(target_flags & MASK_GPOPT)
286 
287 					/* print program statistics */
288 #define TARGET_STATS		(target_flags & MASK_STATS)
289 
290 					/* call memcpy instead of inline code */
291 #define TARGET_MEMCPY		(target_flags & MASK_MEMCPY)
292 
293 					/* .abicalls, etc from Pyramid V.4 */
294 #define TARGET_ABICALLS		(target_flags & MASK_ABICALLS)
295 
296 					/* software floating point */
297 #define TARGET_SOFT_FLOAT	(target_flags & MASK_SOFT_FLOAT)
298 #define TARGET_HARD_FLOAT	(! TARGET_SOFT_FLOAT)
299 
300 					/* always call through a register */
301 #define TARGET_LONG_CALLS	(target_flags & MASK_LONG_CALLS)
302 
303 					/* generate embedded PIC code;
304 					   requires gas.  */
305 #define TARGET_EMBEDDED_PIC	(target_flags & MASK_EMBEDDED_PIC)
306 
307 					/* for embedded systems, optimize for
308 					   reduced RAM space instead of for
309 					   fastest code.  */
310 #define TARGET_EMBEDDED_DATA	(target_flags & MASK_EMBEDDED_DATA)
311 
312 					/* always store uninitialized const
313 					   variables in rodata, requires
314 					   TARGET_EMBEDDED_DATA.  */
315 #define TARGET_UNINIT_CONST_IN_RODATA	(target_flags & MASK_UNINIT_CONST_IN_RODATA)
316 
317 					/* generate big endian code.  */
318 #define TARGET_BIG_ENDIAN	(target_flags & MASK_BIG_ENDIAN)
319 
320 #define TARGET_SINGLE_FLOAT	(target_flags & MASK_SINGLE_FLOAT)
321 #define TARGET_DOUBLE_FLOAT	(! TARGET_SINGLE_FLOAT)
322 
323 #define TARGET_MAD		(target_flags & MASK_MAD)
324 
325 #define TARGET_FUSED_MADD	(! (target_flags & MASK_NO_FUSED_MADD))
326 
327 #define TARGET_4300_MUL_FIX     (target_flags & MASK_4300_MUL_FIX)
328 
329 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
330 #define TARGET_CHECK_RANGE_DIV  (target_flags & MASK_CHECK_RANGE_DIV)
331 
332 #define TARGET_BRANCHLIKELY	(target_flags & MASK_BRANCHLIKELY)
333 
334 /* This is true if we must enable the assembly language file switching
335    code.  */
336 
337 #define TARGET_FILE_SWITCHING \
338   (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
339 
340 /* We must disable the function end stabs when doing the file switching trick,
341    because the Lscope stabs end up in the wrong place, making it impossible
342    to debug the resulting code.  */
343 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
344 
345 					/* Generate mips16 code */
346 #define TARGET_MIPS16		(target_flags & MASK_MIPS16)
347 
348 /* Generic ISA defines.  */
349 #define ISA_MIPS1		    (mips_isa == 1)
350 #define ISA_MIPS2		    (mips_isa == 2)
351 #define ISA_MIPS3                   (mips_isa == 3)
352 #define ISA_MIPS4		    (mips_isa == 4)
353 #define ISA_MIPS32		    (mips_isa == 32)
354 #define ISA_MIPS64                  (mips_isa == 64)
355 
356 /* Architecture target defines.  */
357 #define TARGET_MIPS3900             (mips_arch == PROCESSOR_R3900)
358 #define TARGET_MIPS4000             (mips_arch == PROCESSOR_R4000)
359 #define TARGET_MIPS4100             (mips_arch == PROCESSOR_R4100)
360 #define TARGET_MIPS4120             (mips_arch == PROCESSOR_R4120)
361 #define TARGET_MIPS4300             (mips_arch == PROCESSOR_R4300)
362 #define TARGET_MIPS4KC              (mips_arch == PROCESSOR_R4KC)
363 #define TARGET_MIPS5KC              (mips_arch == PROCESSOR_R5KC)
364 #define TARGET_MIPS5400             (mips_arch == PROCESSOR_R5400)
365 #define TARGET_MIPS5500             (mips_arch == PROCESSOR_R5500)
366 #define TARGET_SB1                  (mips_arch == PROCESSOR_SB1)
367 #define TARGET_SR71K                (mips_arch == PROCESSOR_SR71000)
368 
369 /* Scheduling target defines.  */
370 #define TUNE_MIPS3000               (mips_tune == PROCESSOR_R3000)
371 #define TUNE_MIPS3900               (mips_tune == PROCESSOR_R3900)
372 #define TUNE_MIPS4000               (mips_tune == PROCESSOR_R4000)
373 #define TUNE_MIPS5000               (mips_tune == PROCESSOR_R5000)
374 #define TUNE_MIPS5400               (mips_tune == PROCESSOR_R5400)
375 #define TUNE_MIPS5500               (mips_tune == PROCESSOR_R5500)
376 #define TUNE_MIPS6000               (mips_tune == PROCESSOR_R6000)
377 #define TUNE_SB1                    (mips_tune == PROCESSOR_SB1)
378 #define TUNE_SR71K                  (mips_tune == PROCESSOR_SR71000)
379 
380 /* Define preprocessor macros for the -march and -mtune options.
381    PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
382    processor.  If INFO's canonical name is "foo", define PREFIX to
383    be "foo", and define an additional macro PREFIX_FOO.  */
384 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO)			\
385   do								\
386     {								\
387       char *macro, *p;						\
388 								\
389       macro = concat ((PREFIX), "_", (INFO)->name, NULL);	\
390       for (p = macro; *p != 0; p++)				\
391 	*p = TOUPPER (*p);					\
392 								\
393       builtin_define (macro);					\
394       builtin_define_with_value ((PREFIX), (INFO)->name, 1);	\
395       free (macro);						\
396     }								\
397   while (0)
398 
399 /* Target CPU builtins.  */
400 #define TARGET_CPU_CPP_BUILTINS()				\
401   do								\
402     {								\
403       builtin_assert ("cpu=mips");				\
404       builtin_define ("__mips__");     				\
405       builtin_define ("_mips");					\
406 								\
407       /* We do this here because __mips is defined below	\
408 	 and so we can't use builtin_define_std.  */		\
409       if (!flag_iso)						\
410 	  builtin_define ("mips");				\
411 								\
412       /* Treat _R3000 and _R4000 like register-size defines,	\
413 	 which is how they've historically been used.  */	\
414       if (TARGET_64BIT)						\
415 	{							\
416 	  builtin_define ("__mips64");     			\
417 	  builtin_define ("__mips64__");			\
418 	  builtin_define_std ("R4000");				\
419 	  builtin_define ("_R4000");				\
420 	}							\
421       else							\
422 	{							\
423 	  builtin_define_std ("R3000");				\
424 	  builtin_define ("_R3000");				\
425 	}							\
426       if (TARGET_FLOAT64)					\
427 	  builtin_define ("__mips_fpr=64");			\
428       else							\
429 	  builtin_define ("__mips_fpr=32");			\
430 								\
431       if (TARGET_MIPS16)					\
432 	  builtin_define ("__mips16");				\
433 								\
434       MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info);	\
435       MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info);	\
436 								\
437       if (ISA_MIPS1)						\
438 	{							\
439 	  builtin_define ("__mips=1");				\
440 	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1");		\
441 	}							\
442       else if (ISA_MIPS2)					\
443 	{							\
444 	  builtin_define ("__mips=2");				\
445 	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2");		\
446 	}							\
447       else if (ISA_MIPS3)					\
448 	{							\
449 	  builtin_define ("__mips=3");				\
450 	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3");		\
451 	}							\
452       else if (ISA_MIPS4)					\
453 	{							\
454 	  builtin_define ("__mips=4");				\
455 	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4");		\
456 	}							\
457       else if (ISA_MIPS32)					\
458 	{							\
459 	  builtin_define ("__mips=32");				\
460 	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32");	\
461 	}							\
462       else if (ISA_MIPS64)					\
463 	{							\
464 	  builtin_define ("__mips=64");				\
465 	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64");	\
466 	}							\
467 								\
468       if (TARGET_HARD_FLOAT)					\
469 	  builtin_define ("__mips_hard_float");			\
470       else if (TARGET_SOFT_FLOAT)				\
471 	  builtin_define ("__mips_soft_float");			\
472 								\
473       if (TARGET_SINGLE_FLOAT)					\
474 	  builtin_define ("__mips_single_float");		\
475 								\
476       if (TARGET_BIG_ENDIAN)					\
477 	{							\
478 	  builtin_define_std ("MIPSEB");			\
479 	  builtin_define ("_MIPSEB");				\
480 	}							\
481       else							\
482 	{							\
483 	  builtin_define_std ("MIPSEL");			\
484 	  builtin_define ("_MIPSEL");				\
485 	}							\
486 								\
487         /* Macros dependent on the C dialect.  */		\
488       if (preprocessing_asm_p ())				\
489 	{							\
490           builtin_define_std ("LANGUAGE_ASSEMBLY");		\
491 	  builtin_define ("_LANGUAGE_ASSEMBLY");		\
492 	}							\
493       else if (c_language == clk_c)				\
494 	{							\
495           builtin_define_std ("LANGUAGE_C");			\
496 	  builtin_define ("_LANGUAGE_C");			\
497 	}							\
498       else if (c_language == clk_cplusplus)			\
499         {							\
500 	  builtin_define ("_LANGUAGE_C_PLUS_PLUS");		\
501           builtin_define ("__LANGUAGE_C_PLUS_PLUS");		\
502           builtin_define ("__LANGUAGE_C_PLUS_PLUS__");		\
503         }							\
504       if (flag_objc)						\
505         {							\
506 	  builtin_define ("_LANGUAGE_OBJECTIVE_C");		\
507           builtin_define ("__LANGUAGE_OBJECTIVE_C");		\
508 	  /* Bizzare, but needed at least for Irix.  */		\
509 	  builtin_define_std ("LANGUAGE_C");			\
510 	  builtin_define ("_LANGUAGE_C");			\
511         }							\
512 								\
513       if (mips_abi == ABI_EABI)					\
514 	builtin_define ("__mips_eabi");				\
515 								\
516 } while (0)
517 
518 
519 
520 /* Macro to define tables used to set the flags.
521    This is a list in braces of pairs in braces,
522    each pair being { "NAME", VALUE }
523    where VALUE is the bits to set or minus the bits to clear.
524    An empty string NAME is used to identify the default VALUE.  */
525 
526 #define TARGET_SWITCHES							\
527 {									\
528   {"no-crt0",          0,                                               \
529      N_("No default crt0.o") },					 	\
530   {"int64",		  MASK_INT64 | MASK_LONG64,			\
531      N_("Use 64-bit int type")},					\
532   {"long64",		  MASK_LONG64,					\
533      N_("Use 64-bit long type")},					\
534   {"long32",		 -(MASK_LONG64 | MASK_INT64),			\
535      N_("Use 32-bit long type")},					\
536   {"split-addresses",	  MASK_SPLIT_ADDR,				\
537      N_("Optimize lui/addiu address loads")},				\
538   {"no-split-addresses", -MASK_SPLIT_ADDR,				\
539      N_("Don't optimize lui/addiu address loads")},			\
540   {"mips-as",		 -MASK_GAS,					\
541      N_("Use MIPS as")},						\
542   {"gas",		  MASK_GAS,					\
543      N_("Use GNU as")},							\
544   {"rnames",		  MASK_NAME_REGS,				\
545      N_("Use symbolic register names")},				\
546   {"no-rnames",		 -MASK_NAME_REGS,				\
547      N_("Don't use symbolic register names")},				\
548   {"gpOPT",		  MASK_GPOPT,					\
549      N_("Use GP relative sdata/sbss sections")},			\
550   {"gpopt",		  MASK_GPOPT,					\
551      N_("Use GP relative sdata/sbss sections")},			\
552   {"no-gpOPT",		 -MASK_GPOPT,					\
553      N_("Don't use GP relative sdata/sbss sections")},			\
554   {"no-gpopt",		 -MASK_GPOPT,					\
555      N_("Don't use GP relative sdata/sbss sections")},			\
556   {"stats",		  MASK_STATS,					\
557      N_("Output compiler statistics")},					\
558   {"no-stats",		 -MASK_STATS,					\
559      N_("Don't output compiler statistics")},				\
560   {"memcpy",		  MASK_MEMCPY,					\
561      N_("Don't optimize block moves")},					\
562   {"no-memcpy",		 -MASK_MEMCPY,					\
563      N_("Optimize block moves")},					\
564   {"mips-tfile",	  MASK_MIPS_TFILE,				\
565      N_("Use mips-tfile asm postpass")},				\
566   {"no-mips-tfile",	 -MASK_MIPS_TFILE,				\
567      N_("Don't use mips-tfile asm postpass")},				\
568   {"soft-float",	  MASK_SOFT_FLOAT,				\
569      N_("Use software floating point")},				\
570   {"hard-float",	 -MASK_SOFT_FLOAT,				\
571      N_("Use hardware floating point")},				\
572   {"fp64",		  MASK_FLOAT64,					\
573      N_("Use 64-bit FP registers")},					\
574   {"fp32",		 -MASK_FLOAT64,					\
575      N_("Use 32-bit FP registers")},					\
576   {"gp64",		  MASK_64BIT,					\
577      N_("Use 64-bit general registers")},				\
578   {"gp32",		 -MASK_64BIT,					\
579      N_("Use 32-bit general registers")},				\
580   {"abicalls",		  MASK_ABICALLS,				\
581      N_("Use Irix PIC")},						\
582   {"no-abicalls",	 -MASK_ABICALLS,				\
583      N_("Don't use Irix PIC")},						\
584   {"long-calls",	  MASK_LONG_CALLS,				\
585      N_("Use indirect calls")},						\
586   {"no-long-calls",	 -MASK_LONG_CALLS,				\
587      N_("Don't use indirect calls")},					\
588   {"embedded-pic",	  MASK_EMBEDDED_PIC,				\
589      N_("Use embedded PIC")},						\
590   {"no-embedded-pic",	 -MASK_EMBEDDED_PIC,				\
591      N_("Don't use embedded PIC")},					\
592   {"embedded-data",	  MASK_EMBEDDED_DATA,				\
593      N_("Use ROM instead of RAM")},					\
594   {"no-embedded-data",	 -MASK_EMBEDDED_DATA,				\
595      N_("Don't use ROM instead of RAM")},				\
596   {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA,		\
597      N_("Put uninitialized constants in ROM (needs -membedded-data)")},	\
598   {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA,		\
599      N_("Don't put uninitialized constants in ROM")},			\
600   {"eb",		  MASK_BIG_ENDIAN,				\
601      N_("Use big-endian byte order")},					\
602   {"el",		 -MASK_BIG_ENDIAN,				\
603      N_("Use little-endian byte order")},				\
604   {"single-float",	  MASK_SINGLE_FLOAT,				\
605      N_("Use single (32-bit) FP only")},				\
606   {"double-float",	 -MASK_SINGLE_FLOAT,				\
607      N_("Don't use single (32-bit) FP only")},				\
608   {"mad",		  MASK_MAD,					\
609      N_("Use multiply accumulate")},					\
610   {"no-mad",		 -MASK_MAD,					\
611      N_("Don't use multiply accumulate")},				\
612   {"no-fused-madd",       MASK_NO_FUSED_MADD,                           \
613      N_("Don't generate fused multiply/add instructions")},		\
614   {"fused-madd",         -MASK_NO_FUSED_MADD,                           \
615      N_("Generate fused multiply/add instructions")},			\
616   {"fix4300",             MASK_4300_MUL_FIX,				\
617      N_("Work around early 4300 hardware bug")},			\
618   {"no-fix4300",         -MASK_4300_MUL_FIX,				\
619      N_("Don't work around early 4300 hardware bug")},			\
620   {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV,			\
621      N_("Trap on integer divide by zero")},				\
622   {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV,			\
623      N_("Don't trap on integer divide by zero")},			\
624   {"check-range-division",MASK_CHECK_RANGE_DIV,				\
625      N_("Trap on integer divide overflow")},				\
626   {"no-check-range-division",-MASK_CHECK_RANGE_DIV,			\
627      N_("Don't trap on integer divide overflow")},			\
628   { "branch-likely",      MASK_BRANCHLIKELY,				\
629       N_("Use Branch Likely instructions, overriding default for arch")}, \
630   { "no-branch-likely",  -MASK_BRANCHLIKELY,				\
631       N_("Don't use Branch Likely instructions, overriding default for arch")}, \
632   {"debug",		  MASK_DEBUG,					\
633      NULL},								\
634   {"debuga",		  MASK_DEBUG_A,					\
635      NULL},								\
636   {"debugb",		  MASK_DEBUG_B,					\
637      NULL},								\
638   {"debugc",		  MASK_DEBUG_C,					\
639      NULL},								\
640   {"debugd",		  MASK_DEBUG_D,					\
641      NULL},								\
642   {"debuge",		  MASK_DEBUG_E,					\
643      NULL},								\
644   {"debugf",		  MASK_DEBUG_F,					\
645      NULL},								\
646   {"debugg",		  MASK_DEBUG_G,					\
647      NULL},								\
648   {"debugi",		  MASK_DEBUG_I,					\
649      NULL},								\
650   {"",			  (TARGET_DEFAULT				\
651 			   | TARGET_CPU_DEFAULT				\
652 			   | TARGET_ENDIAN_DEFAULT),			\
653      NULL},								\
654 }
655 
656 /* Default target_flags if no switches are specified  */
657 
658 #ifndef TARGET_DEFAULT
659 #define TARGET_DEFAULT 0
660 #endif
661 
662 #ifndef TARGET_CPU_DEFAULT
663 #define TARGET_CPU_DEFAULT 0
664 #endif
665 
666 #ifndef TARGET_ENDIAN_DEFAULT
667 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
668 #endif
669 
670 /* 'from-abi' makes a good default: you get whatever the ABI requires.  */
671 #ifndef MIPS_ISA_DEFAULT
672 #ifndef MIPS_CPU_STRING_DEFAULT
673 #define MIPS_CPU_STRING_DEFAULT "from-abi"
674 #endif
675 #endif
676 
677 #ifdef IN_LIBGCC2
678 #undef TARGET_64BIT
679 /* Make this compile time constant for libgcc2 */
680 #ifdef __mips64
681 #define TARGET_64BIT		1
682 #else
683 #define TARGET_64BIT		0
684 #endif
685 #endif /* IN_LIBGCC2 */
686 
687 #ifndef MULTILIB_ENDIAN_DEFAULT
688 #if TARGET_ENDIAN_DEFAULT == 0
689 #define MULTILIB_ENDIAN_DEFAULT "EL"
690 #else
691 #define MULTILIB_ENDIAN_DEFAULT "EB"
692 #endif
693 #endif
694 
695 #ifndef MULTILIB_ISA_DEFAULT
696 #  if MIPS_ISA_DEFAULT == 1
697 #    define MULTILIB_ISA_DEFAULT "mips1"
698 #  else
699 #    if MIPS_ISA_DEFAULT == 2
700 #      define MULTILIB_ISA_DEFAULT "mips2"
701 #    else
702 #      if MIPS_ISA_DEFAULT == 3
703 #        define MULTILIB_ISA_DEFAULT "mips3"
704 #      else
705 #        if MIPS_ISA_DEFAULT == 4
706 #          define MULTILIB_ISA_DEFAULT "mips4"
707 #        else
708 #          if MIPS_ISA_DEFAULT == 32
709 #            define MULTILIB_ISA_DEFAULT "mips32"
710 #          else
711 #            if MIPS_ISA_DEFAULT == 64
712 #              define MULTILIB_ISA_DEFAULT "mips64"
713 #            else
714 #          define MULTILIB_ISA_DEFAULT "mips1"
715 #         endif
716 #        endif
717 #       endif
718 #      endif
719 #    endif
720 #  endif
721 #endif
722 
723 #ifndef MULTILIB_DEFAULTS
724 #define MULTILIB_DEFAULTS \
725     { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
726 #endif
727 
728 /* We must pass -EL to the linker by default for little endian embedded
729    targets using linker scripts with a OUTPUT_FORMAT line.  Otherwise, the
730    linker will default to using big-endian output files.  The OUTPUT_FORMAT
731    line must be in the linker script, otherwise -EB/-EL will not work.  */
732 
733 #ifndef ENDIAN_SPEC
734 #if TARGET_ENDIAN_DEFAULT == 0
735 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
736 #else
737 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
738 #endif
739 #endif
740 
741 #define TARGET_OPTIONS							\
742 {									\
743   SUBTARGET_TARGET_OPTIONS						\
744   { "tune=",    &mips_tune_string,			                \
745       N_("Specify CPU for scheduling purposes")},                       \
746   { "arch=",    &mips_arch_string,                                      \
747       N_("Specify CPU for code generation purposes")},                  \
748   { "abi=", &mips_abi_string,						\
749       N_("Specify an ABI")},						\
750   { "ips",	&mips_isa_string,					\
751       N_("Specify a Standard MIPS ISA")},				\
752   { "entry",	&mips_entry_string,					\
753       N_("Use mips16 entry/exit psuedo ops")},				\
754   { "no-mips16", &mips_no_mips16_string,				\
755       N_("Don't use MIPS16 instructions")},				\
756   { "no-flush-func", &mips_cache_flush_func,				\
757       N_("Don't call any cache flush functions")},			\
758   { "flush-func=", &mips_cache_flush_func,				\
759       N_("Specify cache flush function")},				\
760 }
761 
762 /* This is meant to be redefined in the host dependent files.  */
763 #define SUBTARGET_TARGET_OPTIONS
764 
765 #define GENERATE_BRANCHLIKELY   (TARGET_BRANCHLIKELY                    \
766 				 && !TARGET_SR71K                       \
767 				 && !TARGET_MIPS16)
768 
769 /* Generate three-operand multiply instructions for SImode.  */
770 #define GENERATE_MULT3_SI       ((TARGET_MIPS3900                       \
771                                   || TARGET_MIPS5400                    \
772                                   || TARGET_MIPS5500                    \
773                                   || ISA_MIPS32	                        \
774                                   || ISA_MIPS64)                        \
775                                  && !TARGET_MIPS16)
776 
777 /* Generate three-operand multiply instructions for DImode.  */
778 #define GENERATE_MULT3_DI       ((TARGET_MIPS3900)                      \
779 				 && !TARGET_MIPS16)
780 
781 /* Macros to decide whether certain features are available or not,
782    depending on the instruction set architecture level.  */
783 
784 #define HAVE_SQRT_P()		(!ISA_MIPS1)
785 
786 /* True if the ABI can only work with 64-bit integer registers.  We
787    generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
788    otherwise floating-point registers must also be 64-bit.  */
789 #define ABI_NEEDS_64BIT_REGS	(mips_abi == ABI_64			\
790 				 || mips_abi == ABI_O64			\
791 				 || mips_abi == ABI_N32)
792 
793 /* Likewise for 32-bit regs.  */
794 #define ABI_NEEDS_32BIT_REGS	(mips_abi == ABI_32)
795 
796 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3).  */
797 #define ISA_HAS_64BIT_REGS	(ISA_MIPS3				\
798 				 || ISA_MIPS4				\
799                                  || ISA_MIPS64)
800 
801 /* ISA has branch likely instructions (eg. mips2).  */
802 /* Disable branchlikely for tx39 until compare rewrite.  They haven't
803    been generated up to this point.  */
804 #define ISA_HAS_BRANCHLIKELY	(!ISA_MIPS1                             \
805 				 && !TARGET_MIPS5500)
806 
807 /* ISA has the conditional move instructions introduced in mips4.  */
808 #define ISA_HAS_CONDMOVE        ((ISA_MIPS4				\
809 				  || ISA_MIPS32	                        \
810 				  || ISA_MIPS64)			\
811                                  && !TARGET_MIPS5500                    \
812 				 && !TARGET_MIPS16)
813 
814 /* ISA has just the integer condition move instructions (movn,movz) */
815 #define ISA_HAS_INT_CONDMOVE     0
816 
817 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
818    branch on CC, and move (both FP and non-FP) on CC.  */
819 #define ISA_HAS_8CC		(ISA_MIPS4				\
820                          	 || ISA_MIPS32	                        \
821 				 || ISA_MIPS64)
822 
823 /* This is a catch all for the other new mips4 instructions: indexed load and
824    indexed prefetch instructions, the FP madd and msub instructions,
825    and the FP recip and recip sqrt instructions */
826 #define ISA_HAS_FP4             ((ISA_MIPS4				\
827 				  || ISA_MIPS64)       			\
828  				 && !TARGET_MIPS16)
829 
830 /* ISA has conditional trap instructions.  */
831 #define ISA_HAS_COND_TRAP	(!ISA_MIPS1				\
832 				 && !TARGET_MIPS16)
833 
834 /* ISA has integer multiply-accumulate instructions, madd and msub.  */
835 #define ISA_HAS_MADD_MSUB       ((ISA_MIPS32				\
836 				  || ISA_MIPS64				\
837 				  ) && !TARGET_MIPS16)
838 
839 /* ISA has floating-point nmadd and nmsub instructions.  */
840 #define ISA_HAS_NMADD_NMSUB	((ISA_MIPS4				\
841 				  || ISA_MIPS64)       			\
842                                  && (!TARGET_MIPS5400 || TARGET_MAD)    \
843 				 && ! TARGET_MIPS16)
844 
845 /* ISA has count leading zeroes/ones instruction (not implemented).  */
846 #define ISA_HAS_CLZ_CLO         ((ISA_MIPS32				\
847                                   || ISA_MIPS64				\
848                                  ) && !TARGET_MIPS16)
849 
850 /* ISA has double-word count leading zeroes/ones instruction (not
851    implemented).  */
852 #define ISA_HAS_DCLZ_DCLO       (ISA_MIPS64				\
853 				 && !TARGET_MIPS16)
854 
855 /* ISA has three operand multiply instructions that put
856    the high part in an accumulator: mulhi or mulhiu.  */
857 #define ISA_HAS_MULHI           (TARGET_MIPS5400                        \
858                                  || TARGET_MIPS5500                     \
859                                  || TARGET_SR71K                        \
860                                  )
861 
862 /* ISA has three operand multiply instructions that
863    negates the result and puts the result in an accumulator.  */
864 #define ISA_HAS_MULS            (TARGET_MIPS5400                        \
865                                  || TARGET_MIPS5500                     \
866                                  || TARGET_SR71K                        \
867                                  )
868 
869 /* ISA has three operand multiply instructions that subtracts the
870    result from a 4th operand and puts the result in an accumulator.  */
871 #define ISA_HAS_MSAC            (TARGET_MIPS5400                        \
872                                  || TARGET_MIPS5500                     \
873                                  || TARGET_SR71K                        \
874                                  )
875 /* ISA has three operand multiply instructions that  the result
876    from a 4th operand and puts the result in an accumulator.  */
877 #define ISA_HAS_MACC            (TARGET_MIPS5400                        \
878                                  || TARGET_MIPS5500                     \
879                                  || TARGET_SR71K                        \
880                                  )
881 
882 /* ISA has 32-bit rotate right instruction.  */
883 #define ISA_HAS_ROTR_SI         (TARGET_MIPS5400                        \
884                                  || TARGET_MIPS5500                     \
885                                  || TARGET_SR71K                        \
886                                  )
887 
888 /* ISA has 32-bit rotate right instruction.  */
889 #define ISA_HAS_ROTR_DI         (TARGET_64BIT                           \
890                                  && (TARGET_MIPS5400                    \
891                                      || TARGET_MIPS5500                 \
892                                      || TARGET_SR71K                    \
893                                      ))
894 
895 
896 /* ISA has data prefetch instruction.  */
897 #define ISA_HAS_PREFETCH	((ISA_MIPS4				\
898 				  || ISA_MIPS32				\
899 				  || ISA_MIPS64)	       		\
900 				 && !TARGET_MIPS16)
901 
902 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
903    instructions.  Both require TARGET_HARD_FLOAT, and trunc.w.d
904    also requires TARGET_DOUBLE_FLOAT.  */
905 #define ISA_HAS_TRUNC_W		(!ISA_MIPS1)
906 
907 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
908    -mips2 sets -mfp32 and -mgp32.  This can be overridden by an explicit
909    -mfp32, -mfp64, -mgp32 or -mgp64.  -mfp64 sets MASK_FLOAT64 in
910    target_flags, and -mgp64 sets MASK_64BIT.
911 
912    Setting MASK_64BIT in target_flags will cause gcc to assume that
913    registers are 64 bits wide.  int, long and void * will be 32 bit;
914    this may be changed with -mint64 or -mlong64.
915 
916    The gen* programs link code that refers to MASK_64BIT.  They don't
917    actually use the information in target_flags; they just refer to
918    it.  */
919 
920 /* Switch  Recognition by gcc.c.  Add -G xx support */
921 
922 #undef  SWITCH_TAKES_ARG
923 #define SWITCH_TAKES_ARG(CHAR)						\
924   (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
925 
926 /* Sometimes certain combinations of command options do not make sense
927    on a particular target machine.  You can define a macro
928    `OVERRIDE_OPTIONS' to take account of this.  This macro, if
929    defined, is executed once just after all the command options have
930    been parsed.
931 
932    On the MIPS, it is used to handle -G.  We also use it to set up all
933    of the tables referenced in the other macros.  */
934 
935 #define OVERRIDE_OPTIONS override_options ()
936 
937 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
938 
939 /* Show we can debug even without a frame pointer.  */
940 #define CAN_DEBUG_WITHOUT_FP
941 
942 /* Tell collect what flags to pass to nm.  */
943 #ifndef NM_FLAGS
944 #define NM_FLAGS "-Bn"
945 #endif
946 
947 
948 /* Assembler specs.  */
949 
950 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
951    than gas.  */
952 
953 #define MIPS_AS_ASM_SPEC "\
954 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
955 %{pipe: %e-pipe is not supported} \
956 %{K} %(subtarget_mips_as_asm_spec)"
957 
958 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
959    rather than gas.  It may be overridden by subtargets.  */
960 
961 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
962 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
963 #endif
964 
965 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
966    assembler.  */
967 
968 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
969 
970 
971 extern int mips_abi;
972 
973 #ifndef MIPS_ABI_DEFAULT
974 #define MIPS_ABI_DEFAULT ABI_32
975 #endif
976 
977 /* Use the most portable ABI flag for the ASM specs.  */
978 
979 #if MIPS_ABI_DEFAULT == ABI_32
980 #define MULTILIB_ABI_DEFAULT "mabi=32"
981 #define ASM_ABI_DEFAULT_SPEC "-32"
982 #endif
983 
984 #if MIPS_ABI_DEFAULT == ABI_O64
985 #define MULTILIB_ABI_DEFAULT "mabi=o64"
986 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
987 #endif
988 
989 #if MIPS_ABI_DEFAULT == ABI_N32
990 #define MULTILIB_ABI_DEFAULT "mabi=n32"
991 #define ASM_ABI_DEFAULT_SPEC "-n32"
992 #endif
993 
994 #if MIPS_ABI_DEFAULT == ABI_64
995 #define MULTILIB_ABI_DEFAULT "mabi=64"
996 #define ASM_ABI_DEFAULT_SPEC "-64"
997 #endif
998 
999 #if MIPS_ABI_DEFAULT == ABI_EABI
1000 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1001 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1002 #endif
1003 
1004 #if MIPS_ABI_DEFAULT == ABI_MEABI
1005 /* Most GAS don't know about MEABI.  */
1006 #define MULTILIB_ABI_DEFAULT "mabi=meabi"
1007 #define ASM_ABI_DEFAULT_SPEC ""
1008 #endif
1009 
1010 /* Only ELF targets can switch the ABI.  */
1011 #ifndef OBJECT_FORMAT_ELF
1012 #undef ASM_ABI_DEFAULT_SPEC
1013 #define ASM_ABI_DEFAULT_SPEC ""
1014 #endif
1015 
1016 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1017    GAS_ASM_SPEC as the default, depending upon the value of
1018    TARGET_DEFAULT.  */
1019 
1020 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1021 /* GAS */
1022 
1023 #define TARGET_ASM_SPEC "\
1024 %{mmips-as: %(mips_as_asm_spec)} \
1025 %{!mmips-as: %(gas_asm_spec)}"
1026 
1027 #else /* not GAS */
1028 
1029 #define TARGET_ASM_SPEC "\
1030 %{!mgas: %(mips_as_asm_spec)} \
1031 %{mgas: %(gas_asm_spec)}"
1032 
1033 #endif /* not GAS */
1034 
1035 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1036    to the assembler.  It may be overridden by subtargets.  */
1037 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1038 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1039 %{noasmopt:-O0} \
1040 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1041 #endif
1042 
1043 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1044    the assembler.  It may be overridden by subtargets.  */
1045 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1046 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1047 %{g} %{g0} %{g1} %{g2} %{g3} \
1048 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1049 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1050 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1051 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1052 %(mdebug_asm_spec)"
1053 #endif
1054 
1055 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1056    and stabs debugging info.  */
1057 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1058 /* GAS */
1059 #define MDEBUG_ASM_SPEC "%{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
1060 #else /* not GAS */
1061 #define MDEBUG_ASM_SPEC ""
1062 #endif /* not GAS */
1063 
1064 /* SUBTARGET_ASM_SPEC is always passed to the assembler.  It may be
1065    overridden by subtargets.  */
1066 
1067 #ifndef SUBTARGET_ASM_SPEC
1068 #define SUBTARGET_ASM_SPEC ""
1069 #endif
1070 
1071 /* ASM_SPEC is the set of arguments to pass to the assembler.  Note: we
1072    pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1073    whether we're using GAS.  These options can only be used properly
1074    with GAS, and it is better to get an error from a non-GAS assembler
1075    than to silently generate bad code.  */
1076 
1077 #undef ASM_SPEC
1078 #define ASM_SPEC "\
1079 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64}\
1080 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1081 %(subtarget_asm_optimizing_spec) \
1082 %(subtarget_asm_debugging_spec) \
1083 %{membedded-pic} \
1084 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1085 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1086 %{mgp32} %{mgp64} %{march=*} \
1087 %(target_asm_spec) \
1088 %(subtarget_asm_spec)"
1089 
1090 /* Specify to run a post-processor, mips-tfile after the assembler
1091    has run to stuff the mips debug information into the object file.
1092    This is needed because the $#!%^ MIPS assembler provides no way
1093    of specifying such information in the assembly file.  If we are
1094    cross compiling, disable mips-tfile unless the user specifies
1095    -mmips-tfile.  */
1096 
1097 #ifndef ASM_FINAL_SPEC
1098 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1099 /* GAS */
1100 #define ASM_FINAL_SPEC "\
1101 %{mmips-as: %{!mno-mips-tfile: \
1102 	\n mips-tfile %{v*: -v} \
1103 		%{K: -I %b.o~} \
1104 		%{!K: %{save-temps: -I %b.o~}} \
1105 		%{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1106 		%{.s:%i} %{!.s:%g.s}}}"
1107 
1108 #else
1109 /* not GAS */
1110 #define ASM_FINAL_SPEC "\
1111 %{!mgas: %{!mno-mips-tfile: \
1112 	\n mips-tfile %{v*: -v} \
1113 		%{K: -I %b.o~} \
1114 		%{!K: %{save-temps: -I %b.o~}} \
1115 		%{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1116 		%{.s:%i} %{!.s:%g.s}}}"
1117 
1118 #endif
1119 #endif	/* ASM_FINAL_SPEC */
1120 
1121 /* Redefinition of libraries used.  Mips doesn't support normal
1122    UNIX style profiling via calling _mcount.  It does offer
1123    profiling that samples the PC, so do what we can...  */
1124 
1125 #ifndef LIB_SPEC
1126 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
1127 #endif
1128 
1129 /* Extra switches sometimes passed to the linker.  */
1130 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1131   will interpret it as a -b option.  */
1132 
1133 #ifndef LINK_SPEC
1134 #define LINK_SPEC "\
1135 %(endian_spec) \
1136 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} \
1137 %{bestGnum} %{shared} %{non_shared}"
1138 #endif  /* LINK_SPEC defined */
1139 
1140 
1141 /* Specs for the compiler proper */
1142 
1143 /* SUBTARGET_CC1_SPEC is passed to the compiler proper.  It may be
1144    overridden by subtargets.  */
1145 #ifndef SUBTARGET_CC1_SPEC
1146 #define SUBTARGET_CC1_SPEC ""
1147 #endif
1148 
1149 /* CC1_SPEC is the set of arguments to pass to the compiler proper.  */
1150 /* Note, we will need to adjust the following if we ever find a MIPS variant
1151    that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1152    that show up in this case.  */
1153 
1154 #ifndef CC1_SPEC
1155 #define CC1_SPEC "\
1156 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1157 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1158 %{save-temps: } \
1159 %(subtarget_cc1_spec)"
1160 #endif
1161 
1162 /* Preprocessor specs.  */
1163 
1164 /* SUBTARGET_CPP_SPEC is passed to the preprocessor.  It may be
1165    overridden by subtargets.  */
1166 #ifndef SUBTARGET_CPP_SPEC
1167 #define SUBTARGET_CPP_SPEC ""
1168 #endif
1169 
1170 #define CPP_SPEC "%(subtarget_cpp_spec)"
1171 
1172 /* This macro defines names of additional specifications to put in the specs
1173    that can be used in various specifications like CC1_SPEC.  Its definition
1174    is an initializer with a subgrouping for each command option.
1175 
1176    Each subgrouping contains a string constant, that defines the
1177    specification name, and a string constant that used by the GNU CC driver
1178    program.
1179 
1180    Do not define this macro if it does not need to do anything.  */
1181 
1182 #define EXTRA_SPECS							\
1183   { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC },				\
1184   { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },				\
1185   { "mips_as_asm_spec", MIPS_AS_ASM_SPEC },				\
1186   { "gas_asm_spec", GAS_ASM_SPEC },					\
1187   { "target_asm_spec", TARGET_ASM_SPEC },				\
1188   { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, 	\
1189   { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC },	\
1190   { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC },	\
1191   { "mdebug_asm_spec", MDEBUG_ASM_SPEC },				\
1192   { "subtarget_asm_spec", SUBTARGET_ASM_SPEC },				\
1193   { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC },			\
1194   { "endian_spec", ENDIAN_SPEC },					\
1195   SUBTARGET_EXTRA_SPECS
1196 
1197 #ifndef SUBTARGET_EXTRA_SPECS
1198 #define SUBTARGET_EXTRA_SPECS
1199 #endif
1200 
1201 /* If defined, this macro is an additional prefix to try after
1202    `STANDARD_EXEC_PREFIX'.  */
1203 
1204 #ifndef MD_EXEC_PREFIX
1205 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1206 #endif
1207 
1208 #ifndef MD_STARTFILE_PREFIX
1209 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1210 #endif
1211 
1212 
1213 /* Print subsidiary information on the compiler version in use.  */
1214 
1215 #define MIPS_VERSION "[AL 1.1, MM 40]"
1216 
1217 #ifndef MACHINE_TYPE
1218 #define MACHINE_TYPE "BSD Mips"
1219 #endif
1220 
1221 #ifndef TARGET_VERSION_INTERNAL
1222 #define TARGET_VERSION_INTERNAL(STREAM)					\
1223   fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1224 #endif
1225 
1226 #ifndef TARGET_VERSION
1227 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1228 #endif
1229 
1230 
1231 #define SDB_DEBUGGING_INFO 1		/* generate info for mips-tfile */
1232 #define DBX_DEBUGGING_INFO 1		/* generate stabs (OSF/rose) */
1233 #define MIPS_DEBUGGING_INFO 1		/* MIPS specific debugging info */
1234 
1235 #ifndef PREFERRED_DEBUGGING_TYPE	/* assume SDB_DEBUGGING_INFO */
1236 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1237 #endif
1238 
1239 /* By default, turn on GDB extensions.  */
1240 #define DEFAULT_GDB_EXTENSIONS 1
1241 
1242 /* If we are passing smuggling stabs through the MIPS ECOFF object
1243    format, put a comment in front of the .stab<x> operation so
1244    that the MIPS assembler does not choke.  The mips-tfile program
1245    will correctly put the stab into the object file.  */
1246 
1247 #define ASM_STABS_OP	((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1248 #define ASM_STABN_OP	((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1249 #define ASM_STABD_OP	((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1250 
1251 /* Local compiler-generated symbols must have a prefix that the assembler
1252    understands.   By default, this is $, although some targets (e.g.,
1253    NetBSD-ELF) need to override this.  */
1254 
1255 #ifndef LOCAL_LABEL_PREFIX
1256 #define LOCAL_LABEL_PREFIX	"$"
1257 #endif
1258 
1259 /* By default on the mips, external symbols do not have an underscore
1260    prepended, but some targets (e.g., NetBSD) require this.  */
1261 
1262 #ifndef USER_LABEL_PREFIX
1263 #define USER_LABEL_PREFIX	""
1264 #endif
1265 
1266 /* Forward references to tags are allowed.  */
1267 #define SDB_ALLOW_FORWARD_REFERENCES
1268 
1269 /* Unknown tags are also allowed.  */
1270 #define SDB_ALLOW_UNKNOWN_REFERENCES
1271 
1272 /* On Sun 4, this limit is 2048.  We use 1500 to be safe,
1273    since the length can run past this up to a continuation point.  */
1274 #undef DBX_CONTIN_LENGTH
1275 #define DBX_CONTIN_LENGTH 1500
1276 
1277 /* How to renumber registers for dbx and gdb.  */
1278 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1279 
1280 /* The mapping from gcc register number to DWARF 2 CFA column number.
1281    This mapping does not allow for tracking register 0, since SGI's broken
1282    dwarf reader thinks column 0 is used for the frame address, but since
1283    register 0 is fixed this is not a problem.  */
1284 #define DWARF_FRAME_REGNUM(REG)				\
1285   (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1286 
1287 /* The DWARF 2 CFA column which tracks the return address.  */
1288 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1289 
1290 /* Before the prologue, RA lives in r31.  */
1291 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1292 
1293 /* Describe how we implement __builtin_eh_return.  */
1294 #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1295 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1296 
1297 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1298    The default for this in 64-bit mode is 8, which causes problems with
1299    SFmode register saves.  */
1300 #define DWARF_CIE_DATA_ALIGNMENT 4
1301 
1302 /* Overrides for the COFF debug format.  */
1303 #define PUT_SDB_SCL(a)					\
1304 do {							\
1305   extern FILE *asm_out_text_file;			\
1306   fprintf (asm_out_text_file, "\t.scl\t%d;", (a));	\
1307 } while (0)
1308 
1309 #define PUT_SDB_INT_VAL(a)				\
1310 do {							\
1311   extern FILE *asm_out_text_file;			\
1312   fprintf (asm_out_text_file, "\t.val\t");		\
1313   fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1314   fprintf (asm_out_text_file, ";");			\
1315 } while (0)
1316 
1317 #define PUT_SDB_VAL(a)					\
1318 do {							\
1319   extern FILE *asm_out_text_file;			\
1320   fputs ("\t.val\t", asm_out_text_file);		\
1321   output_addr_const (asm_out_text_file, (a));		\
1322   fputc (';', asm_out_text_file);			\
1323 } while (0)
1324 
1325 #define PUT_SDB_DEF(a)					\
1326 do {							\
1327   extern FILE *asm_out_text_file;			\
1328   fprintf (asm_out_text_file, "\t%s.def\t",		\
1329 	   (TARGET_GAS) ? "" : "#");			\
1330   ASM_OUTPUT_LABELREF (asm_out_text_file, a); 		\
1331   fputc (';', asm_out_text_file);			\
1332 } while (0)
1333 
1334 #define PUT_SDB_PLAIN_DEF(a)				\
1335 do {							\
1336   extern FILE *asm_out_text_file;			\
1337   fprintf (asm_out_text_file, "\t%s.def\t.%s;",		\
1338 	   (TARGET_GAS) ? "" : "#", (a));		\
1339 } while (0)
1340 
1341 #define PUT_SDB_ENDEF					\
1342 do {							\
1343   extern FILE *asm_out_text_file;			\
1344   fprintf (asm_out_text_file, "\t.endef\n");		\
1345 } while (0)
1346 
1347 #define PUT_SDB_TYPE(a)					\
1348 do {							\
1349   extern FILE *asm_out_text_file;			\
1350   fprintf (asm_out_text_file, "\t.type\t0x%x;", (a));	\
1351 } while (0)
1352 
1353 #define PUT_SDB_SIZE(a)					\
1354 do {							\
1355   extern FILE *asm_out_text_file;			\
1356   fprintf (asm_out_text_file, "\t.size\t");		\
1357   fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1358   fprintf (asm_out_text_file, ";");			\
1359 } while (0)
1360 
1361 #define PUT_SDB_DIM(a)					\
1362 do {							\
1363   extern FILE *asm_out_text_file;			\
1364   fprintf (asm_out_text_file, "\t.dim\t%d;", (a));	\
1365 } while (0)
1366 
1367 #ifndef PUT_SDB_START_DIM
1368 #define PUT_SDB_START_DIM				\
1369 do {							\
1370   extern FILE *asm_out_text_file;			\
1371   fprintf (asm_out_text_file, "\t.dim\t");		\
1372 } while (0)
1373 #endif
1374 
1375 #ifndef PUT_SDB_NEXT_DIM
1376 #define PUT_SDB_NEXT_DIM(a)				\
1377 do {							\
1378   extern FILE *asm_out_text_file;			\
1379   fprintf (asm_out_text_file, "%d,", a);		\
1380 } while (0)
1381 #endif
1382 
1383 #ifndef PUT_SDB_LAST_DIM
1384 #define PUT_SDB_LAST_DIM(a)				\
1385 do {							\
1386   extern FILE *asm_out_text_file;			\
1387   fprintf (asm_out_text_file, "%d;", a);		\
1388 } while (0)
1389 #endif
1390 
1391 #define PUT_SDB_TAG(a)					\
1392 do {							\
1393   extern FILE *asm_out_text_file;			\
1394   fprintf (asm_out_text_file, "\t.tag\t");		\
1395   ASM_OUTPUT_LABELREF (asm_out_text_file, a); 		\
1396   fputc (';', asm_out_text_file);			\
1397 } while (0)
1398 
1399 /* For block start and end, we create labels, so that
1400    later we can figure out where the correct offset is.
1401    The normal .ent/.end serve well enough for functions,
1402    so those are just commented out.  */
1403 
1404 #define PUT_SDB_BLOCK_START(LINE)			\
1405 do {							\
1406   extern FILE *asm_out_text_file;			\
1407   fprintf (asm_out_text_file,				\
1408 	   "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n",		\
1409 	   LOCAL_LABEL_PREFIX,				\
1410 	   sdb_label_count,				\
1411 	   (TARGET_GAS) ? "" : "#",			\
1412 	   LOCAL_LABEL_PREFIX,				\
1413 	   sdb_label_count,				\
1414 	   (LINE));					\
1415   sdb_label_count++;					\
1416 } while (0)
1417 
1418 #define PUT_SDB_BLOCK_END(LINE)				\
1419 do {							\
1420   extern FILE *asm_out_text_file;			\
1421   fprintf (asm_out_text_file,				\
1422 	   "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n",		\
1423 	   LOCAL_LABEL_PREFIX,				\
1424 	   sdb_label_count,				\
1425 	   (TARGET_GAS) ? "" : "#",			\
1426 	   LOCAL_LABEL_PREFIX,				\
1427 	   sdb_label_count,				\
1428 	   (LINE));					\
1429   sdb_label_count++;					\
1430 } while (0)
1431 
1432 #define PUT_SDB_FUNCTION_START(LINE)
1433 
1434 #define PUT_SDB_FUNCTION_END(LINE)			\
1435 do {							\
1436   extern FILE *asm_out_text_file;			\
1437   ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1438 } while (0)
1439 
1440 #define PUT_SDB_EPILOGUE_END(NAME)
1441 
1442 #define PUT_SDB_SRC_FILE(FILENAME)			\
1443 do {							\
1444   extern FILE *asm_out_text_file;			\
1445   output_file_directive (asm_out_text_file, (FILENAME));\
1446 } while (0)
1447 
1448 #define SDB_GENERATE_FAKE(BUFFER, NUMBER)		\
1449   sprintf ((BUFFER), ".%dfake", (NUMBER));
1450 
1451 /* Correct the offset of automatic variables and arguments.  Note that
1452    the MIPS debug format wants all automatic variables and arguments
1453    to be in terms of the virtual frame pointer (stack pointer before
1454    any adjustment in the function), while the MIPS 3.0 linker wants
1455    the frame pointer to be the stack pointer after the initial
1456    adjustment.  */
1457 
1458 #define DEBUGGER_AUTO_OFFSET(X)				\
1459   mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1460 #define DEBUGGER_ARG_OFFSET(OFFSET, X)			\
1461   mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1462 
1463 /* Tell collect that the object format is ECOFF */
1464 #define OBJECT_FORMAT_COFF	/* Object file looks like COFF */
1465 #define EXTENDED_COFF		/* ECOFF, not normal coff */
1466 
1467 /* Target machine storage layout */
1468 
1469 /* Define this if most significant bit is lowest numbered
1470    in instructions that operate on numbered bit-fields.
1471 */
1472 #define BITS_BIG_ENDIAN 0
1473 
1474 /* Define this if most significant byte of a word is the lowest numbered.  */
1475 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1476 
1477 /* Define this if most significant word of a multiword number is the lowest.  */
1478 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1479 
1480 /* Define this to set the endianness to use in libgcc2.c, which can
1481    not depend on target_flags.  */
1482 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1483 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1484 #else
1485 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1486 #endif
1487 
1488 #define MAX_BITS_PER_WORD 64
1489 
1490 /* Width of a word, in units (bytes).  */
1491 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1492 #define MIN_UNITS_PER_WORD 4
1493 
1494 /* For MIPS, width of a floating point register.  */
1495 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1496 
1497 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1498    the next available register.  */
1499 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1500 
1501 /* The largest size of value that can be held in floating-point
1502    registers and moved with a single instruction.  */
1503 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1504 
1505 /* The largest size of value that can be held in floating-point
1506    registers.  */
1507 #define UNITS_PER_FPVALUE \
1508   (TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
1509 
1510 /* The number of bytes in a double.  */
1511 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1512 
1513 /* A C expression for the size in bits of the type `int' on the
1514    target machine.  If you don't define this, the default is one
1515    word.  */
1516 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1517 
1518 /* Tell the preprocessor the maximum size of wchar_t.  */
1519 #ifndef MAX_WCHAR_TYPE_SIZE
1520 #ifndef WCHAR_TYPE_SIZE
1521 #define MAX_WCHAR_TYPE_SIZE 64
1522 #endif
1523 #endif
1524 
1525 /* A C expression for the size in bits of the type `short' on the
1526    target machine.  If you don't define this, the default is half a
1527    word.  (If this would be less than one storage unit, it is
1528    rounded up to one unit.)  */
1529 #define SHORT_TYPE_SIZE 16
1530 
1531 /* A C expression for the size in bits of the type `long' on the
1532    target machine.  If you don't define this, the default is one
1533    word.  */
1534 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1535 #define MAX_LONG_TYPE_SIZE 64
1536 
1537 /* A C expression for the size in bits of the type `long long' on the
1538    target machine.  If you don't define this, the default is two
1539    words.  */
1540 #define LONG_LONG_TYPE_SIZE 64
1541 
1542 /* A C expression for the size in bits of the type `float' on the
1543    target machine.  If you don't define this, the default is one
1544    word.  */
1545 #define FLOAT_TYPE_SIZE 32
1546 
1547 /* A C expression for the size in bits of the type `double' on the
1548    target machine.  If you don't define this, the default is two
1549    words.  */
1550 #define DOUBLE_TYPE_SIZE 64
1551 
1552 /* A C expression for the size in bits of the type `long double' on
1553    the target machine.  If you don't define this, the default is two
1554    words.  */
1555 #define LONG_DOUBLE_TYPE_SIZE \
1556   (mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
1557 
1558 /* long double is not a fixed mode, but the idea is that, if we
1559    support long double, we also want a 128-bit integer type.  */
1560 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1561 
1562 #ifdef IN_LIBGCC2
1563 #if  (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1564   || (defined _ABI64 && _MIPS_SIM == _ABI64)
1565 #  define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1566 # else
1567 #  define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1568 # endif
1569 #endif
1570 
1571 /* Width in bits of a pointer.
1572    See also the macro `Pmode' defined below.  */
1573 #ifndef POINTER_SIZE
1574 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1575 #endif
1576 
1577 /* Allocation boundary (in *bits*) for storing pointers in memory.  */
1578 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1579 
1580 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
1581 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1582 			|| mips_abi == ABI_64 \
1583 			|| (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1584 
1585 /* Allocation boundary (in *bits*) for the code of a function.  */
1586 #define FUNCTION_BOUNDARY 32
1587 
1588 /* Alignment of field after `int : 0' in a structure.  */
1589 #define EMPTY_FIELD_BOUNDARY 32
1590 
1591 /* Every structure's size must be a multiple of this.  */
1592 /* 8 is observed right on a DECstation and on riscos 4.02.  */
1593 #define STRUCTURE_SIZE_BOUNDARY 8
1594 
1595 /* There is no point aligning anything to a rounder boundary than this.  */
1596 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1597 
1598 /* Set this nonzero if move instructions will actually fail to work
1599    when given unaligned data.  */
1600 #define STRICT_ALIGNMENT 1
1601 
1602 /* Define this if you wish to imitate the way many other C compilers
1603    handle alignment of bitfields and the structures that contain
1604    them.
1605 
1606    The behavior is that the type written for a bit-field (`int',
1607    `short', or other integer type) imposes an alignment for the
1608    entire structure, as if the structure really did contain an
1609    ordinary field of that type.  In addition, the bit-field is placed
1610    within the structure so that it would fit within such a field,
1611    not crossing a boundary for it.
1612 
1613    Thus, on most machines, a bit-field whose type is written as `int'
1614    would not cross a four-byte boundary, and would force four-byte
1615    alignment for the whole structure.  (The alignment used may not
1616    be four bytes; it is controlled by the other alignment
1617    parameters.)
1618 
1619    If the macro is defined, its definition should be a C expression;
1620    a nonzero value for the expression enables this behavior.  */
1621 
1622 #define PCC_BITFIELD_TYPE_MATTERS 1
1623 
1624 /* If defined, a C expression to compute the alignment given to a
1625    constant that is being placed in memory.  CONSTANT is the constant
1626    and ALIGN is the alignment that the object would ordinarily have.
1627    The value of this macro is used instead of that alignment to align
1628    the object.
1629 
1630    If this macro is not defined, then ALIGN is used.
1631 
1632    The typical use of this macro is to increase alignment for string
1633    constants to be word aligned so that `strcpy' calls that copy
1634    constants can be done inline.  */
1635 
1636 #define CONSTANT_ALIGNMENT(EXP, ALIGN)					\
1637   ((TREE_CODE (EXP) == STRING_CST  || TREE_CODE (EXP) == CONSTRUCTOR)	\
1638    && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1639 
1640 /* If defined, a C expression to compute the alignment for a static
1641    variable.  TYPE is the data type, and ALIGN is the alignment that
1642    the object would ordinarily have.  The value of this macro is used
1643    instead of that alignment to align the object.
1644 
1645    If this macro is not defined, then ALIGN is used.
1646 
1647    One use of this macro is to increase alignment of medium-size
1648    data to make it all fit in fewer cache lines.  Another is to
1649    cause character arrays to be word-aligned so that `strcpy' calls
1650    that copy constants to character arrays can be done inline.  */
1651 
1652 #undef DATA_ALIGNMENT
1653 #define DATA_ALIGNMENT(TYPE, ALIGN)					\
1654   ((((ALIGN) < BITS_PER_WORD)						\
1655     && (TREE_CODE (TYPE) == ARRAY_TYPE					\
1656 	|| TREE_CODE (TYPE) == UNION_TYPE				\
1657 	|| TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1658 
1659 
1660 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1661 
1662 #define PAD_VARARGS_DOWN (TARGET_64BIT                                  \
1663 			  || mips_abi == ABI_MEABI                      \
1664 			     ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1665 
1666 /* Define this macro if an argument declared as `char' or `short' in a
1667    prototype should actually be passed as an `int'.  In addition to
1668    avoiding errors in certain cases of mismatch, it also makes for
1669    better code on certain machines.  */
1670 
1671 #define PROMOTE_PROTOTYPES 1
1672 
1673 /* Define if operations between registers always perform the operation
1674    on the full register even if a narrower mode is specified.  */
1675 #define WORD_REGISTER_OPERATIONS
1676 
1677 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1678    will either zero-extend or sign-extend.  The value of this macro should
1679    be the code that says which one of the two operations is implicitly
1680    done, NIL if none.
1681 
1682    When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1683    moves.  All other referces are zero extended.  */
1684 #define LOAD_EXTEND_OP(MODE) \
1685   (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1686    ? SIGN_EXTEND : ZERO_EXTEND)
1687 
1688 /* Define this macro if it is advisable to hold scalars in registers
1689    in a wider mode than that declared by the program.  In such cases,
1690    the value is constrained to be within the bounds of the declared
1691    type, but kept valid in the wider mode.  The signedness of the
1692    extension may differ from that of the type.
1693 
1694    We promote any value smaller than SImode up to SImode.  We don't
1695    want to promote to DImode when in 64 bit mode, because that would
1696    prevent us from using the faster SImode multiply and divide
1697    instructions.  */
1698 
1699 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)	\
1700   if (GET_MODE_CLASS (MODE) == MODE_INT		\
1701       && GET_MODE_SIZE (MODE) < 4)		\
1702     (MODE) = SImode;
1703 
1704 /* Define this if function arguments should also be promoted using the above
1705    procedure.  */
1706 
1707 #define PROMOTE_FUNCTION_ARGS
1708 
1709 /* Likewise, if the function return value is promoted.  */
1710 
1711 #define PROMOTE_FUNCTION_RETURN
1712 
1713 /* Standard register usage.  */
1714 
1715 /* Number of actual hardware registers.
1716    The hardware registers are assigned numbers for the compiler
1717    from 0 to just below FIRST_PSEUDO_REGISTER.
1718    All registers that the compiler knows about must be given numbers,
1719    even those that are not normally considered general registers.
1720 
1721    On the Mips, we have 32 integer registers, 32 floating point
1722    registers, 8 condition code registers, and the special registers
1723    hi, lo, hilo, and rap.  Afetr that we have 32 COP0 registers, 32
1724    COP2 registers, and 32 COp3 registers.  (COP1 is the floating-point
1725    processor.)  The 8 condition code registers are only used if
1726    mips_isa >= 4.  The hilo register is only used in 64 bit mode.  It
1727    represents a 64 bit value stored as two 32 bit values in the hi and
1728    lo registers; this is the result of the mult instruction.  rap is a
1729    pointer to the stack where the return address reg ($31) was stored.
1730    This is needed for C++ exception handling.  */
1731 
1732 #define FIRST_PSEUDO_REGISTER 176
1733 
1734 /* 1 for registers that have pervasive standard uses
1735    and are not available for the register allocator.
1736 
1737    On the MIPS, see conventions, page D-2  */
1738 
1739 /* Regarding coprocessor registers: without evidence to the contrary,
1740    it's best to assume that each coprocessor register has a unique
1741    use.  This can be overridden, in, e.g., override_options() or
1742    CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1743    for a particular target.  */
1744 
1745 #define FIXED_REGISTERS							\
1746 {									\
1747   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
1748   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1,			\
1749   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
1750   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
1751   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,			\
1752   /* COP0 registers */							\
1753   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
1754   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
1755   /* COP2 registers */							\
1756   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
1757   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
1758   /* COP3 registers */							\
1759   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
1760   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1			\
1761 }
1762 
1763 
1764 /* 1 for registers not available across function calls.
1765    These must include the FIXED_REGISTERS and also any
1766    registers that can be used without being saved.
1767    The latter must include the registers where values are returned
1768    and the register where structure-value addresses are passed.
1769    Aside from that, you can include as many other registers as you like.  */
1770 
1771 #define CALL_USED_REGISTERS						\
1772 {									\
1773   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
1774   0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1,			\
1775   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
1776   1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
1777   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0,			\
1778   /* COP0 registers */							\
1779   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
1780   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
1781   /* COP2 registers */							\
1782   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
1783   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
1784   /* COP3 registers */							\
1785   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
1786   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1			\
1787 }
1788 
1789 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1790    problem which makes CALL_USED_REGISTERS *always* include
1791    all the FIXED_REGISTERS.  Until this problem has been
1792    resolved this macro can be used to overcome this situation.
1793    In particular, block_propagate() requires this list
1794    be acurate, or we can remove registers which should be live.
1795    This macro is used in regs_invalidated_by_call.  */
1796 
1797 
1798 #define CALL_REALLY_USED_REGISTERS                                      \
1799 { /* General registers.  */                                             \
1800   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1801   0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1,                       \
1802   /* Floating-point registers.  */                                      \
1803   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
1804   1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
1805   /* Others.  */                                                        \
1806   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0,			\
1807   /* COP0 registers */							\
1808   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
1809   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
1810   /* COP2 registers */							\
1811   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
1812   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
1813   /* COP3 registers */							\
1814   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
1815   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0			\
1816 }
1817 
1818 /* Internal macros to classify a register number as to whether it's a
1819    general purpose register, a floating point register, a
1820    multiply/divide register, or a status register.  */
1821 
1822 #define GP_REG_FIRST 0
1823 #define GP_REG_LAST  31
1824 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
1825 #define GP_DBX_FIRST 0
1826 
1827 #define FP_REG_FIRST 32
1828 #define FP_REG_LAST  63
1829 #define FP_REG_NUM   (FP_REG_LAST - FP_REG_FIRST + 1)
1830 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1831 
1832 #define MD_REG_FIRST 64
1833 #define MD_REG_LAST  66
1834 #define MD_REG_NUM   (MD_REG_LAST - MD_REG_FIRST + 1)
1835 
1836 #define ST_REG_FIRST 67
1837 #define ST_REG_LAST  74
1838 #define ST_REG_NUM   (ST_REG_LAST - ST_REG_FIRST + 1)
1839 
1840 #define RAP_REG_NUM   75
1841 
1842 #define COP0_REG_FIRST 80
1843 #define COP0_REG_LAST 111
1844 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1845 
1846 #define COP2_REG_FIRST 112
1847 #define COP2_REG_LAST 143
1848 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1849 
1850 #define COP3_REG_FIRST 144
1851 #define COP3_REG_LAST 175
1852 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1853 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively.  */
1854 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1855 
1856 #define AT_REGNUM	(GP_REG_FIRST + 1)
1857 #define HI_REGNUM	(MD_REG_FIRST + 0)
1858 #define LO_REGNUM	(MD_REG_FIRST + 1)
1859 #define HILO_REGNUM	(MD_REG_FIRST + 2)
1860 
1861 /* FPSW_REGNUM is the single condition code used if mips_isa < 4.  If
1862    mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1863    should be used instead.  */
1864 #define FPSW_REGNUM	ST_REG_FIRST
1865 
1866 #define GP_REG_P(REGNO)	\
1867   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1868 #define M16_REG_P(REGNO) \
1869   (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1870 #define FP_REG_P(REGNO)  \
1871   ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1872 #define MD_REG_P(REGNO) \
1873   ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1874 #define ST_REG_P(REGNO) \
1875   ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1876 #define COP0_REG_P(REGNO) \
1877   ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1878 #define COP2_REG_P(REGNO) \
1879   ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1880 #define COP3_REG_P(REGNO) \
1881   ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1882 #define ALL_COP_REG_P(REGNO) \
1883   ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1884 
1885 /* Return coprocessor number from register number.  */
1886 
1887 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) 				\
1888   (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2'			\
1889    : COP3_REG_P (REGNO) ? '3' : '?')
1890 
1891 /* Return number of consecutive hard regs needed starting at reg REGNO
1892    to hold something of mode MODE.
1893    This is ordinarily the length in words of a value of mode MODE
1894    but can be less for certain modes in special long registers.
1895 
1896    On the MIPS, all general registers are one word long.  Except on
1897    the R4000 with the FR bit set, the floating point uses register
1898    pairs, with the second register not being allocable.  */
1899 
1900 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1901 
1902 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1903    MODE.  In 32 bit mode, require that DImode and DFmode be in even
1904    registers.  For DImode, this makes some of the insns easier to
1905    write, since you don't have to worry about a DImode value in
1906    registers 3 & 4, producing a result in 4 & 5.
1907 
1908    To make the code simpler HARD_REGNO_MODE_OK now just references an
1909    array built in override_options.  Because machmodes.h is not yet
1910    included before this file is processed, the MODE bound can't be
1911    expressed here.  */
1912 
1913 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1914 
1915 #define HARD_REGNO_MODE_OK(REGNO, MODE)					\
1916   mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1917 
1918 /* Value is 1 if it is a good idea to tie two pseudo registers
1919    when one has mode MODE1 and one has mode MODE2.
1920    If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1921    for any hard reg, then this must be 0 for correct output.  */
1922 #define MODES_TIEABLE_P(MODE1, MODE2)					\
1923   ((GET_MODE_CLASS (MODE1) == MODE_FLOAT ||				\
1924     GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)			\
1925    == (GET_MODE_CLASS (MODE2) == MODE_FLOAT ||				\
1926        GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1927 
1928 /* MIPS pc is not overloaded on a register.	*/
1929 /* #define PC_REGNUM xx				*/
1930 
1931 /* Register to use for pushing function arguments.  */
1932 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1933 
1934 /* Offset from the stack pointer to the first available location.  Use
1935    the default value zero.  */
1936 /* #define STACK_POINTER_OFFSET 0 */
1937 
1938 /* Base register for access to local variables of the function.  We
1939    pretend that the frame pointer is $1, and then eliminate it to
1940    HARD_FRAME_POINTER_REGNUM.  We can get away with this because $1 is
1941    a fixed register, and will not be used for anything else.  */
1942 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1943 
1944 /* Temporary scratch register for use by the assembler.  */
1945 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1946 
1947 /* $30 is not available on the mips16, so we use $17 as the frame
1948    pointer.  */
1949 #define HARD_FRAME_POINTER_REGNUM \
1950   (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1951 
1952 /* Value should be nonzero if functions must have frame pointers.
1953    Zero means the frame pointer need not be set up (and parms
1954    may be accessed via the stack pointer) in functions that seem suitable.
1955    This is computed in `reload', in reload1.c.  */
1956 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1957 
1958 /* Base register for access to arguments of the function.  */
1959 #define ARG_POINTER_REGNUM GP_REG_FIRST
1960 
1961 /* Fake register that holds the address on the stack of the
1962    current function's return address.  */
1963 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1964 
1965 /* Register in which static-chain is passed to a function.  */
1966 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1967 
1968 /* If the structure value address is passed in a register, then
1969    `STRUCT_VALUE_REGNUM' should be the number of that register.  */
1970 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1971 
1972 /* If the structure value address is not passed in a register, define
1973    `STRUCT_VALUE' as an expression returning an RTX for the place
1974    where the address is passed.  If it returns 0, the address is
1975    passed as an "invisible" first argument.  */
1976 #define STRUCT_VALUE 0
1977 
1978 /* Mips registers used in prologue/epilogue code when the stack frame
1979    is larger than 32K bytes.  These registers must come from the
1980    scratch register set, and not used for passing and returning
1981    arguments and any other information used in the calling sequence
1982    (such as pic).  Must start at 12, since t0/t3 are parameter passing
1983    registers in the 64 bit ABI.  */
1984 
1985 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1986 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1987 
1988 /* Define this macro if it is as good or better to call a constant
1989    function address than to call an address kept in a register.  */
1990 #define NO_FUNCTION_CSE 1
1991 
1992 /* Define this macro if it is as good or better for a function to
1993    call itself with an explicit address than to call an address
1994    kept in a register.  */
1995 #define NO_RECURSIVE_FUNCTION_CSE 1
1996 
1997 /* The register number of the register used to address a table of
1998    static data addresses in memory.  In some cases this register is
1999    defined by a processor's "application binary interface" (ABI).
2000    When this macro is defined, RTL is generated for this register
2001    once, as with the stack pointer and frame pointer registers.  If
2002    this macro is not defined, it is up to the machine-dependent
2003    files to allocate such a register (if necessary).  */
2004 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
2005 
2006 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
2007 
2008 /* Define the classes of registers for register constraints in the
2009    machine description.  Also define ranges of constants.
2010 
2011    One of the classes must always be named ALL_REGS and include all hard regs.
2012    If there is more than one class, another class must be named NO_REGS
2013    and contain no registers.
2014 
2015    The name GENERAL_REGS must be the name of a class (or an alias for
2016    another name such as ALL_REGS).  This is the class of registers
2017    that is allowed by "g" or "r" in a register constraint.
2018    Also, registers outside this class are allocated only when
2019    instructions express preferences for them.
2020 
2021    The classes must be numbered in nondecreasing order; that is,
2022    a larger-numbered class must never be contained completely
2023    in a smaller-numbered class.
2024 
2025    For any two classes, it is very desirable that there be another
2026    class that represents their union.  */
2027 
2028 enum reg_class
2029 {
2030   NO_REGS,			/* no registers in set */
2031   M16_NA_REGS,			/* mips16 regs not used to pass args */
2032   M16_REGS,			/* mips16 directly accessible registers */
2033   T_REG,			/* mips16 T register ($24) */
2034   M16_T_REGS,			/* mips16 registers plus T register */
2035   GR_REGS,			/* integer registers */
2036   FP_REGS,			/* floating point registers */
2037   HI_REG,			/* hi register */
2038   LO_REG,			/* lo register */
2039   HILO_REG,			/* hilo register pair for 64 bit mode mult */
2040   MD_REGS,			/* multiply/divide registers (hi/lo) */
2041   COP0_REGS,			/* generic coprocessor classes */
2042   COP2_REGS,
2043   COP3_REGS,
2044   HI_AND_GR_REGS,		/* union classes */
2045   LO_AND_GR_REGS,
2046   HILO_AND_GR_REGS,
2047   HI_AND_FP_REGS,
2048   COP0_AND_GR_REGS,
2049   COP2_AND_GR_REGS,
2050   COP3_AND_GR_REGS,
2051   ALL_COP_REGS,
2052   ALL_COP_AND_GR_REGS,
2053   ST_REGS,			/* status registers (fp status) */
2054   ALL_REGS,			/* all registers */
2055   LIM_REG_CLASSES		/* max value + 1 */
2056 };
2057 
2058 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2059 
2060 #define GENERAL_REGS GR_REGS
2061 
2062 /* An initializer containing the names of the register classes as C
2063    string constants.  These names are used in writing some of the
2064    debugging dumps.  */
2065 
2066 #define REG_CLASS_NAMES							\
2067 {									\
2068   "NO_REGS",								\
2069   "M16_NA_REGS",							\
2070   "M16_REGS",								\
2071   "T_REG",								\
2072   "M16_T_REGS",								\
2073   "GR_REGS",								\
2074   "FP_REGS",								\
2075   "HI_REG",								\
2076   "LO_REG",								\
2077   "HILO_REG",								\
2078   "MD_REGS",								\
2079   /* coprocessor registers */						\
2080   "COP0_REGS",								\
2081   "COP2_REGS",								\
2082   "COP3_REGS",								\
2083   "HI_AND_GR_REGS",							\
2084   "LO_AND_GR_REGS",							\
2085   "HILO_AND_GR_REGS",							\
2086   "HI_AND_FP_REGS",							\
2087   "COP0_AND_GR_REGS",							\
2088   "COP2_AND_GR_REGS",							\
2089   "COP3_AND_GR_REGS",							\
2090   "ALL_COP_REGS",							\
2091   "ALL_COP_AND_GR_REGS",						\
2092   "ST_REGS",								\
2093   "ALL_REGS"								\
2094 }
2095 
2096 /* An initializer containing the contents of the register classes,
2097    as integers which are bit masks.  The Nth integer specifies the
2098    contents of class N.  The way the integer MASK is interpreted is
2099    that register R is in the class if `MASK & (1 << R)' is 1.
2100 
2101    When the machine has more than 32 registers, an integer does not
2102    suffice.  Then the integers are replaced by sub-initializers,
2103    braced groupings containing several integers.  Each
2104    sub-initializer must be suitable as an initializer for the type
2105    `HARD_REG_SET' which is defined in `hard-reg-set.h'.  */
2106 
2107 #define REG_CLASS_CONTENTS						\
2108 {									\
2109   { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* no registers */	\
2110   { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* mips16 nonarg regs */\
2111   { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* mips16 registers */	\
2112   { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* mips16 T register */	\
2113   { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* mips16 and T regs */ \
2114   { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* integer registers */	\
2115   { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* floating registers*/	\
2116   { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 },	/* hi register */	\
2117   { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 },	/* lo register */	\
2118   { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 },	/* hilo register */	\
2119   { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 },	/* mul/div registers */	\
2120   { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
2121   { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
2122   { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
2123   { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 },	/* union classes */     \
2124   { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 },				\
2125   { 0xffffffff, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 },				\
2126   { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 },				\
2127   { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 },			\
2128   { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 },	\
2129   { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
2130   { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2131   { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2132   { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 },	/* status registers */	\
2133   { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff }	/* all registers */	\
2134 }
2135 
2136 
2137 /* A C expression whose value is a register class containing hard
2138    register REGNO.  In general there is more that one such class;
2139    choose a class which is "minimal", meaning that no smaller class
2140    also contains the register.  */
2141 
2142 extern const enum reg_class mips_regno_to_class[];
2143 
2144 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2145 
2146 /* A macro whose definition is the name of the class to which a
2147    valid base register must belong.  A base register is one used in
2148    an address which is the register value plus a displacement.  */
2149 
2150 #define BASE_REG_CLASS  (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2151 
2152 /* A macro whose definition is the name of the class to which a
2153    valid index register must belong.  An index register is one used
2154    in an address where its value is either multiplied by a scale
2155    factor or added to another register (as well as added to a
2156    displacement).  */
2157 
2158 #define INDEX_REG_CLASS NO_REGS
2159 
2160 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2161    registers explicitly used in the rtl to be used as spill registers
2162    but prevents the compiler from extending the lifetime of these
2163    registers.  */
2164 
2165 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2166 
2167 /* This macro is used later on in the file.  */
2168 #define GR_REG_CLASS_P(CLASS)						\
2169   ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG	\
2170    || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
2171 
2172 /* This macro is also used later on in the file.  */
2173 #define COP_REG_CLASS_P(CLASS)						\
2174   ((CLASS)  == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
2175 
2176 /* REG_ALLOC_ORDER is to order in which to allocate registers.  This
2177    is the default value (allocate the registers in numeric order).  We
2178    define it just so that we can override it for the mips16 target in
2179    ORDER_REGS_FOR_LOCAL_ALLOC.  */
2180 
2181 #define REG_ALLOC_ORDER							\
2182 {  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,	\
2183   16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,	\
2184   32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,	\
2185   48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,	\
2186   64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,	\
2187   80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,	\
2188   96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111,	\
2189   112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,	\
2190   128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,	\
2191   144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,	\
2192   160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175	\
2193 }
2194 
2195 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2196    to be rearranged based on a particular function.  On the mips16, we
2197    want to allocate $24 (T_REG) before other registers for
2198    instructions for which it is possible.  */
2199 
2200 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2201 
2202 /* REGISTER AND CONSTANT CLASSES */
2203 
2204 /* Get reg_class from a letter such as appears in the machine
2205    description.
2206 
2207    DEFINED REGISTER CLASSES:
2208 
2209    'd'  General (aka integer) registers
2210         Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2211    'y'  General registers (in both mips16 and non mips16 mode)
2212    'e'	mips16 non argument registers (M16_NA_REGS)
2213    't'  mips16 temporary register ($24)
2214    'f'	Floating point registers
2215    'h'	Hi register
2216    'l'	Lo register
2217    'x'	Multiply/divide registers
2218    'a'	HILO_REG
2219    'z'	FP Status register
2220    'B'  Cop0 register
2221    'C'  Cop2 register
2222    'D'  Cop3 register
2223    'b'	All registers */
2224 
2225 extern enum reg_class mips_char_to_class[256];
2226 
2227 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2228 
2229 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2230    string can be used to stand for particular ranges of immediate
2231    operands.  This macro defines what the ranges are.  C is the
2232    letter, and VALUE is a constant value.  Return 1 if VALUE is
2233    in the range specified by C.  */
2234 
2235 /* For MIPS:
2236 
2237    `I'	is used for the range of constants an arithmetic insn can
2238 	actually contain (16 bits signed integers).
2239 
2240    `J'	is used for the range which is just zero (ie, $r0).
2241 
2242    `K'	is used for the range of constants a logical insn can actually
2243 	contain (16 bit zero-extended integers).
2244 
2245    `L'	is used for the range of constants that be loaded with lui
2246 	(ie, the bottom 16 bits are zero).
2247 
2248    `M'	is used for the range of constants that take two words to load
2249 	(ie, not matched by `I', `K', and `L').
2250 
2251    `N'	is used for negative 16 bit constants other than -65536.
2252 
2253    `O'	is a 15 bit signed integer.
2254 
2255    `P'	is used for positive 16 bit constants.  */
2256 
2257 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
2258 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
2259 
2260 #define CONST_OK_FOR_LETTER_P(VALUE, C)					\
2261   ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000)	\
2262    : (C) == 'J' ? ((VALUE) == 0)					\
2263    : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000)		\
2264    : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0				\
2265 		   && (((VALUE) & ~2147483647) == 0			\
2266 		       || ((VALUE) & ~2147483647) == ~2147483647))	\
2267    : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0)			\
2268 		   && (((VALUE) & ~0x0000ffff) != ~0x0000ffff)		\
2269 		   && (((VALUE) & 0x0000ffff) != 0			\
2270 		       || (((VALUE) & ~2147483647) != 0			\
2271 			   && ((VALUE) & ~2147483647) != ~2147483647)))	\
2272    : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2273    : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2274    : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0))	\
2275    : 0)
2276 
2277 /* Similar, but for floating constants, and defining letters G and H.
2278    Here VALUE is the CONST_DOUBLE rtx itself.  */
2279 
2280 /* For Mips
2281 
2282   'G'	: Floating point 0 */
2283 
2284 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)				\
2285   ((C) == 'G'								\
2286    && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2287 
2288 /* Letters in the range `Q' through `U' may be defined in a
2289    machine-dependent fashion to stand for arbitrary operand types.
2290    The machine description macro `EXTRA_CONSTRAINT' is passed the
2291    operand as its first argument and the constraint letter as its
2292    second operand.
2293 
2294    `Q'	is for mips16 GP relative constants
2295    `R'	is for memory references which take 1 word for the instruction.
2296    `T'	is for memory addresses that can be used to load two words.  */
2297 
2298 #define EXTRA_CONSTRAINT(OP,CODE)					\
2299   (((CODE) == 'T')	  ? double_memory_operand (OP, GET_MODE (OP))	\
2300    : ((CODE) == 'Q')	  ? (GET_CODE (OP) == CONST			\
2301 			     && mips16_gp_offset_p (OP))		\
2302    : (GET_CODE (OP) != MEM) ? FALSE					\
2303    : ((CODE) == 'R')	  ? simple_memory_operand (OP, GET_MODE (OP))	\
2304    : FALSE)
2305 
2306 /* Given an rtx X being reloaded into a reg required to be
2307    in class CLASS, return the class of reg to actually use.
2308    In general this is just CLASS; but on some machines
2309    in some cases it is preferable to use a more restrictive class.  */
2310 
2311 #define PREFERRED_RELOAD_CLASS(X,CLASS)					\
2312   ((CLASS) != ALL_REGS							\
2313    ? (! TARGET_MIPS16							\
2314       ? (CLASS)								\
2315       : ((CLASS) != GR_REGS						\
2316 	 ? (CLASS)							\
2317 	 : M16_REGS))							\
2318    : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT			\
2319        || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT)		\
2320       ? (TARGET_SOFT_FLOAT						\
2321 	 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS)				\
2322 	 : FP_REGS)							\
2323       : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT			\
2324 	  || GET_MODE (X) == VOIDmode)					\
2325 	 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS)				\
2326 	 : (CLASS))))
2327 
2328 /* Certain machines have the property that some registers cannot be
2329    copied to some other registers without using memory.  Define this
2330    macro on those machines to be a C expression that is nonzero if
2331    objects of mode MODE in registers of CLASS1 can only be copied to
2332    registers of class CLASS2 by storing a register of CLASS1 into
2333    memory and loading that memory location into a register of CLASS2.
2334 
2335    Do not define this macro if its value would always be zero.  */
2336 #if 0
2337 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE)			\
2338   ((!TARGET_DEBUG_H_MODE						\
2339     && GET_MODE_CLASS (MODE) == MODE_INT				\
2340     && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2))			\
2341 	|| (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS)))		\
2342    || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode		\
2343        && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS)		\
2344 	   || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2345 #endif
2346 /* The HI and LO registers can only be reloaded via the general
2347    registers.  Condition code registers can only be loaded to the
2348    general registers, and from the floating point registers.  */
2349 
2350 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X)			\
2351   mips_secondary_reload_class (CLASS, MODE, X, 1)
2352 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X)			\
2353   mips_secondary_reload_class (CLASS, MODE, X, 0)
2354 
2355 /* Return the maximum number of consecutive registers
2356    needed to represent mode MODE in a register of class CLASS.  */
2357 
2358 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2359 
2360 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2361   mips_cannot_change_mode_class (FROM, TO, CLASS)
2362 
2363 /* Stack layout; function entry, exit and calling.  */
2364 
2365 /* Define this if pushing a word on the stack
2366    makes the stack pointer a smaller address.  */
2367 #define STACK_GROWS_DOWNWARD
2368 
2369 /* Define this if the nominal address of the stack frame
2370    is at the high-address end of the local variables;
2371    that is, each additional local variable allocated
2372    goes at a more negative offset in the frame.  */
2373 /* #define FRAME_GROWS_DOWNWARD */
2374 
2375 /* Offset within stack frame to start allocating local variables at.
2376    If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2377    first local allocated.  Otherwise, it is the offset to the BEGINNING
2378    of the first local allocated.  */
2379 #define STARTING_FRAME_OFFSET						\
2380   (current_function_outgoing_args_size					\
2381    + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2382 
2383 /* Offset from the stack pointer register to an item dynamically
2384    allocated on the stack, e.g., by `alloca'.
2385 
2386    The default value for this macro is `STACK_POINTER_OFFSET' plus the
2387    length of the outgoing arguments.  The default is correct for most
2388    machines.  See `function.c' for details.
2389 
2390    The MIPS ABI states that functions which dynamically allocate the
2391    stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2392    we are trying to create a second frame pointer to the function, so
2393    allocate some stack space to make it happy.
2394 
2395    However, the linker currently complains about linking any code that
2396    dynamically allocates stack space, and there seems to be a bug in
2397    STACK_DYNAMIC_OFFSET, so don't define this right now.  */
2398 
2399 #if 0
2400 #define STACK_DYNAMIC_OFFSET(FUNDECL)					\
2401   ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2402 	? 4*UNITS_PER_WORD						\
2403 	: current_function_outgoing_args_size)
2404 #endif
2405 
2406 /* The return address for the current frame is in r31 if this is a leaf
2407    function.  Otherwise, it is on the stack.  It is at a variable offset
2408    from sp/fp/ap, so we define a fake hard register rap which is a
2409    poiner to the return address on the stack.  This always gets eliminated
2410    during reload to be either the frame pointer or the stack pointer plus
2411    an offset.  */
2412 
2413 /* ??? This definition fails for leaf functions.  There is currently no
2414    general solution for this problem.  */
2415 
2416 /* ??? There appears to be no way to get the return address of any previous
2417    frame except by disassembling instructions in the prologue/epilogue.
2418    So currently we support only the current frame.  */
2419 
2420 #define RETURN_ADDR_RTX(count, frame)					\
2421   (((count) == 0)							\
2422    ? (leaf_function_p ()						\
2423       ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31)				\
2424       : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode,				\
2425 					 RETURN_ADDRESS_POINTER_REGNUM))) \
2426    : (rtx) 0)
2427 
2428 /* Since the mips16 ISA mode is encoded in the least-significant bit
2429    of the address, mask it off return addresses for purposes of
2430    finding exception handling regions.  */
2431 
2432 #define MASK_RETURN_ADDR GEN_INT (-2)
2433 
2434 /* Similarly, don't use the least-significant bit to tell pointers to
2435    code from vtable index.  */
2436 
2437 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2438 
2439 /* If defined, this macro specifies a table of register pairs used to
2440    eliminate unneeded registers that point into the stack frame.  If
2441    it is not defined, the only elimination attempted by the compiler
2442    is to replace references to the frame pointer with references to
2443    the stack pointer.
2444 
2445    The definition of this macro is a list of structure
2446    initializations, each of which specifies an original and
2447    replacement register.
2448 
2449    On some machines, the position of the argument pointer is not
2450    known until the compilation is completed.  In such a case, a
2451    separate hard register must be used for the argument pointer.
2452    This register can be eliminated by replacing it with either the
2453    frame pointer or the argument pointer, depending on whether or not
2454    the frame pointer has been eliminated.
2455 
2456    In this case, you might specify:
2457         #define ELIMINABLE_REGS  \
2458         {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2459          {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2460          {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2461 
2462    Note that the elimination of the argument pointer with the stack
2463    pointer is specified first since that is the preferred elimination.
2464 
2465    The eliminations to $17 are only used on the mips16.  See the
2466    definition of HARD_FRAME_POINTER_REGNUM.  */
2467 
2468 #define ELIMINABLE_REGS							\
2469 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},				\
2470  { ARG_POINTER_REGNUM,   GP_REG_FIRST + 30},				\
2471  { ARG_POINTER_REGNUM,   GP_REG_FIRST + 17},				\
2472  { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM},		\
2473  { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30},			\
2474  { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17},			\
2475  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},				\
2476  { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30},				\
2477  { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2478 
2479 /* A C expression that returns nonzero if the compiler is allowed to
2480    try to replace register number FROM-REG with register number
2481    TO-REG.  This macro need only be defined if `ELIMINABLE_REGS' is
2482    defined, and will usually be the constant 1, since most of the
2483    cases preventing register elimination are things that the compiler
2484    already knows about.
2485 
2486    When not in mips16 and mips64, we can always eliminate to the
2487    frame pointer.  We can eliminate to the stack pointer unless
2488    a frame pointer is needed.  In mips16 mode, we need a frame
2489    pointer for a large frame; otherwise, reload may be unable
2490    to compute the address of a local variable, since there is
2491    no way to add a large constant to the stack pointer
2492    without using a temporary register.
2493 
2494    In mips16, for some instructions (eg lwu), we can't eliminate the
2495    frame pointer for the stack pointer.  These instructions are
2496    only generated in TARGET_64BIT mode.
2497    */
2498 
2499 #define CAN_ELIMINATE(FROM, TO)						\
2500   (((FROM) == RETURN_ADDRESS_POINTER_REGNUM				\
2501     && (((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed)	\
2502  	|| (TO) == HARD_FRAME_POINTER_REGNUM))				\
2503    || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM				\
2504       && ((TO) == HARD_FRAME_POINTER_REGNUM 				\
2505 	  || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed	\
2506 	      && ! (TARGET_MIPS16 && TARGET_64BIT)			\
2507 	      && (! TARGET_MIPS16					\
2508 	          || compute_frame_size (get_frame_size ()) < 32768)))))
2509 
2510 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2511 	(OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2512 
2513 /* If we generate an insn to push BYTES bytes,
2514    this says how many the stack pointer really advances by.
2515    On the VAX, sp@- in a byte insn really pushes a word.  */
2516 
2517 /* #define PUSH_ROUNDING(BYTES) 0 */
2518 
2519 /* If defined, the maximum amount of space required for outgoing
2520    arguments will be computed and placed into the variable
2521    `current_function_outgoing_args_size'.  No space will be pushed
2522    onto the stack for each call; instead, the function prologue
2523    should increase the stack frame size by this amount.
2524 
2525    It is not proper to define both `PUSH_ROUNDING' and
2526    `ACCUMULATE_OUTGOING_ARGS'.  */
2527 #define ACCUMULATE_OUTGOING_ARGS 1
2528 
2529 /* Offset from the argument pointer register to the first argument's
2530    address.  On some machines it may depend on the data type of the
2531    function.
2532 
2533    If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2534    the first argument's address.
2535 
2536    On the MIPS, we must skip the first argument position if we are
2537    returning a structure or a union, to account for its address being
2538    passed in $4.  However, at the current time, this produces a compiler
2539    that can't bootstrap, so comment it out for now.  */
2540 
2541 #if 0
2542 #define FIRST_PARM_OFFSET(FNDECL)					\
2543   (FNDECL != 0								\
2544    && TREE_TYPE (FNDECL) != 0						\
2545    && TREE_TYPE (TREE_TYPE (FNDECL)) != 0				\
2546    && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE	\
2547        || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE)	\
2548 		? UNITS_PER_WORD					\
2549 		: 0)
2550 #else
2551 #define FIRST_PARM_OFFSET(FNDECL) 0
2552 #endif
2553 
2554 /* When a parameter is passed in a register, stack space is still
2555    allocated for it.  For the MIPS, stack space must be allocated, cf
2556    Asm Lang Prog Guide page 7-8.
2557 
2558    BEWARE that some space is also allocated for non existing arguments
2559    in register. In case an argument list is of form GF used registers
2560    are a0 (a2,a3), but we should push over a1...  */
2561 
2562 #define REG_PARM_STACK_SPACE(FNDECL) 					 \
2563   ((mips_abi == ABI_32 || mips_abi == ABI_O64)				 \
2564    ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
2565    : 0)
2566 
2567 /* Define this if it is the responsibility of the caller to
2568    allocate the area reserved for arguments passed in registers.
2569    If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2570    of this macro is to determine whether the space is included in
2571    `current_function_outgoing_args_size'.  */
2572 #define OUTGOING_REG_PARM_STACK_SPACE
2573 
2574 #define STACK_BOUNDARY \
2575   ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2576    ? 64 : 128)
2577 
2578 /* Make sure 4 words are always allocated on the stack.  */
2579 
2580 #ifndef STACK_ARGS_ADJUST
2581 #define STACK_ARGS_ADJUST(SIZE)						\
2582 {									\
2583   if (SIZE.constant < 4 * UNITS_PER_WORD)				\
2584     SIZE.constant = 4 * UNITS_PER_WORD;					\
2585 }
2586 #endif
2587 
2588 
2589 /* A C expression that should indicate the number of bytes of its
2590    own arguments that a function pops on returning, or 0
2591    if the function pops no arguments and the caller must therefore
2592    pop them all after the function returns.
2593 
2594    FUNDECL is the declaration node of the function (as a tree).
2595 
2596    FUNTYPE is a C variable whose value is a tree node that
2597    describes the function in question.  Normally it is a node of
2598    type `FUNCTION_TYPE' that describes the data type of the function.
2599    From this it is possible to obtain the data types of the value
2600    and arguments (if known).
2601 
2602    When a call to a library function is being considered, FUNTYPE
2603    will contain an identifier node for the library function.  Thus,
2604    if you need to distinguish among various library functions, you
2605    can do so by their names.  Note that "library function" in this
2606    context means a function used to perform arithmetic, whose name
2607    is known specially in the compiler and was not mentioned in the
2608    C code being compiled.
2609 
2610    STACK-SIZE is the number of bytes of arguments passed on the
2611    stack.  If a variable number of bytes is passed, it is zero, and
2612    argument popping will always be the responsibility of the
2613    calling function.  */
2614 
2615 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2616 
2617 
2618 /* Symbolic macros for the registers used to return integer and floating
2619    point values.  */
2620 
2621 #define GP_RETURN (GP_REG_FIRST + 2)
2622 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2623 
2624 #define MAX_ARGS_IN_REGISTERS \
2625   ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2626 
2627 /* Largest possible value of MAX_ARGS_IN_REGISTERS.  */
2628 
2629 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2630 
2631 /* Symbolic macros for the first/last argument registers.  */
2632 
2633 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2634 #define GP_ARG_LAST  (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2635 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2636 #define FP_ARG_LAST  (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2637 
2638 /* Define how to find the value returned by a library function
2639    assuming the value has mode MODE.  Because we define
2640    PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2641    PROMOTE_MODE does.  */
2642 
2643 #define LIBCALL_VALUE(MODE) \
2644   mips_function_value (NULL_TREE, NULL, (MODE))
2645 
2646 /* Define how to find the value returned by a function.
2647    VALTYPE is the data type of the value (as a tree).
2648    If the precise function being called is known, FUNC is its FUNCTION_DECL;
2649    otherwise, FUNC is 0.  */
2650 
2651 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2652   mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2653 
2654 /* 1 if N is a possible register number for a function value.
2655    On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2656    Currently, R2 and F0 are only implemented  here (C has no complex type)  */
2657 
2658 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2659   || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2660       && (N) == FP_RETURN + 2))
2661 
2662 /* 1 if N is a possible register number for function argument passing.
2663    We have no FP argument registers when soft-float.  When FP registers
2664    are 32 bits, we can't directly reference the odd numbered ones.  */
2665 
2666 #define FUNCTION_ARG_REGNO_P(N)					\
2667   ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST)			\
2668     || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST)		\
2669 	&& ((N) % FP_INC == 0) && mips_abi != ABI_O64))		\
2670    && !fixed_regs[N])
2671 
2672 /* A C expression which can inhibit the returning of certain function
2673    values in registers, based on the type of value.  A nonzero value says
2674    to return the function value in memory, just as large structures are
2675    always returned.  Here TYPE will be a C expression of type
2676    `tree', representing the data type of the value.
2677 
2678    Note that values of mode `BLKmode' must be explicitly
2679    handled by this macro.  Also, the option `-fpcc-struct-return'
2680    takes effect regardless of this macro.  On most systems, it is
2681    possible to leave the macro undefined; this causes a default
2682    definition to be used, whose value is the constant 1 for BLKmode
2683    values, and 0 otherwise.
2684 
2685    GCC normally converts 1 byte structures into chars, 2 byte
2686    structs into shorts, and 4 byte structs into ints, and returns
2687    them this way.  Defining the following macro overrides this,
2688    to give us MIPS cc compatibility.  */
2689 
2690 #define RETURN_IN_MEMORY(TYPE)	\
2691 	mips_return_in_memory (TYPE)
2692 
2693 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL)	\
2694 	(PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE),	\
2695 						      (TYPE), (NO_RTL))
2696 
2697 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2698 
2699 /* Define a data type for recording info about an argument list
2700    during the scan of that argument list.  This data type should
2701    hold all necessary information about the function itself
2702    and about the args processed so far, enough to enable macros
2703    such as FUNCTION_ARG to determine where the next arg should go.
2704 
2705    This structure has to cope with two different argument allocation
2706    schemes.  Most MIPS ABIs view the arguments as a struct, of which the
2707    first N words go in registers and the rest go on the stack.  If I < N,
2708    the Ith word might go in Ith integer argument register or the
2709    Ith floating-point one.  In some cases, it has to go in both (see
2710    function_arg).  For these ABIs, we only need to remember the number
2711    of words passed so far.
2712 
2713    The EABI instead allocates the integer and floating-point arguments
2714    separately.  The first N words of FP arguments go in FP registers,
2715    the rest go on the stack.  Likewise, the first N words of the other
2716    arguments go in integer registers, and the rest go on the stack.  We
2717    need to maintain three counts: the number of integer registers used,
2718    the number of floating-point registers used, and the number of words
2719    passed on the stack.
2720 
2721    We could keep separate information for the two ABIs (a word count for
2722    the standard ABIs, and three separate counts for the EABI).  But it
2723    seems simpler to view the standard ABIs as forms of EABI that do not
2724    allocate floating-point registers.
2725 
2726    So for the standard ABIs, the first N words are allocated to integer
2727    registers, and function_arg decides on an argument-by-argument basis
2728    whether that argument should really go in an integer register, or in
2729    a floating-point one.  */
2730 
2731 typedef struct mips_args {
2732   /* Always true for varargs functions.  Otherwise true if at least
2733      one argument has been passed in an integer register.  */
2734   int gp_reg_found;
2735 
2736   /* The number of arguments seen so far.  */
2737   unsigned int arg_number;
2738 
2739   /* For EABI, the number of integer registers used so far.  For other
2740      ABIs, the number of words passed in registers (whether integer
2741      or floating-point).  */
2742   unsigned int num_gprs;
2743 
2744   /* For EABI, the number of floating-point registers used so far.  */
2745   unsigned int num_fprs;
2746 
2747   /* The number of words passed on the stack.  */
2748   unsigned int stack_words;
2749 
2750   /* On the mips16, we need to keep track of which floating point
2751      arguments were passed in general registers, but would have been
2752      passed in the FP regs if this were a 32 bit function, so that we
2753      can move them to the FP regs if we wind up calling a 32 bit
2754      function.  We record this information in fp_code, encoded in base
2755      four.  A zero digit means no floating point argument, a one digit
2756      means an SFmode argument, and a two digit means a DFmode argument,
2757      and a three digit is not used.  The low order digit is the first
2758      argument.  Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2759      an SFmode argument.  ??? A more sophisticated approach will be
2760      needed if MIPS_ABI != ABI_32.  */
2761   int fp_code;
2762 
2763   /* True if the function has a prototype.  */
2764   int prototype;
2765 
2766   /* When a structure does not take up a full register, the argument
2767      should sometimes be shifted left so that it occupies the high part
2768      of the register.  These two fields describe an array of ashl
2769      patterns for doing this.  See function_arg_advance, which creates
2770      the shift patterns, and function_arg, which returns them when given
2771      a VOIDmode argument.  */
2772   unsigned int num_adjusts;
2773   rtx adjust[BIGGEST_MAX_ARGS_IN_REGISTERS];
2774 } CUMULATIVE_ARGS;
2775 
2776 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2777    for a call to a function whose data type is FNTYPE.
2778    For a library call, FNTYPE is 0.
2779 
2780 */
2781 
2782 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)		\
2783   init_cumulative_args (&CUM, FNTYPE, LIBNAME)				\
2784 
2785 /* Update the data in CUM to advance over an argument
2786    of mode MODE and data type TYPE.
2787    (TYPE is null for libcalls where that information may not be available.)  */
2788 
2789 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)			\
2790   function_arg_advance (&CUM, MODE, TYPE, NAMED)
2791 
2792 /* Determine where to put an argument to a function.
2793    Value is zero to push the argument on the stack,
2794    or a hard register in which to store the argument.
2795 
2796    MODE is the argument's machine mode.
2797    TYPE is the data type of the argument (as a tree).
2798     This is null for libcalls where that information may
2799     not be available.
2800    CUM is a variable of type CUMULATIVE_ARGS which gives info about
2801     the preceding args and about the function being called.
2802    NAMED is nonzero if this argument is a named parameter
2803     (otherwise it is an extra parameter matching an ellipsis).  */
2804 
2805 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2806   function_arg( &CUM, MODE, TYPE, NAMED)
2807 
2808 /* For an arg passed partly in registers and partly in memory,
2809    this is the number of registers used.
2810    For args passed entirely in registers or entirely in memory, zero.  */
2811 
2812 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2813   function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2814 
2815 /* If defined, a C expression that gives the alignment boundary, in
2816    bits, of an argument with the specified mode and type.  If it is
2817    not defined,  `PARM_BOUNDARY' is used for all arguments.  */
2818 
2819 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE)				\
2820   (((TYPE) != 0)							\
2821 	? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY)				\
2822 		? PARM_BOUNDARY						\
2823 		: TYPE_ALIGN(TYPE))					\
2824 	: ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY)			\
2825 		? PARM_BOUNDARY						\
2826 		: GET_MODE_ALIGNMENT(MODE)))
2827 
2828 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED)		\
2829   function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2830 
2831 #define FUNCTION_ARG_PADDING(MODE, TYPE)				\
2832   (! BYTES_BIG_ENDIAN							\
2833    ? upward								\
2834    : (((MODE) == BLKmode						\
2835        ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST		\
2836 	  && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
2837        : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY			\
2838 	  && (mips_abi == ABI_32					\
2839 	      || mips_abi == ABI_O64					\
2840 	      || mips_abi == ABI_EABI					\
2841 	      || GET_MODE_CLASS (MODE) == MODE_INT)))			\
2842       ? downward : upward))
2843 
2844 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED)		\
2845   (mips_abi == ABI_EABI && (NAMED)					\
2846    && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2847 
2848 /* Modified version of the macro in expr.h.  */
2849 #define MUST_PASS_IN_STACK(MODE,TYPE)			\
2850   ((TYPE) != 0						\
2851    && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST	\
2852        || TREE_ADDRESSABLE (TYPE)			\
2853        || ((MODE) == BLKmode 				\
2854 	   && mips_abi != ABI_32 && mips_abi != ABI_O64 \
2855 	   && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2856 		 && 0 == (int_size_in_bytes (TYPE)	\
2857 			  % (PARM_BOUNDARY / BITS_PER_UNIT))) \
2858 	   && (FUNCTION_ARG_PADDING (MODE, TYPE)	\
2859 	       == (BYTES_BIG_ENDIAN ? upward : downward)))))
2860 
2861 /* True if using EABI and varargs can be passed in floating-point
2862    registers.  Under these conditions, we need a more complex form
2863    of va_list, which tracks GPR, FPR and stack arguments separately.  */
2864 #define EABI_FLOAT_VARARGS_P \
2865 	(mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2866 
2867 
2868 /* Tell prologue and epilogue if register REGNO should be saved / restored.  */
2869 
2870 #define MUST_SAVE_REGISTER(regno) \
2871  ((regs_ever_live[regno] && !call_used_regs[regno])			\
2872   || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)	\
2873   || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2874 
2875 /* Treat LOC as a byte offset from the stack pointer and round it up
2876    to the next fully-aligned offset.  */
2877 #define MIPS_STACK_ALIGN(LOC)						\
2878   ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)	\
2879    ? ((LOC) + 7) & ~7							\
2880    : ((LOC) + 15) & ~15)
2881 
2882 
2883 /* Define the `__builtin_va_list' type for the ABI.  */
2884 #define BUILD_VA_LIST_TYPE(VALIST) \
2885   (VALIST) = mips_build_va_list ()
2886 
2887 /* Implement `va_start' for varargs and stdarg.  */
2888 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2889   mips_va_start (valist, nextarg)
2890 
2891 /* Implement `va_arg'.  */
2892 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2893   mips_va_arg (valist, type)
2894 
2895 /* Output assembler code to FILE to increment profiler label # LABELNO
2896    for profiling a function entry.  */
2897 
2898 #define FUNCTION_PROFILER(FILE, LABELNO)				\
2899 {									\
2900   if (TARGET_MIPS16)							\
2901     sorry ("mips16 function profiling");				\
2902   fprintf (FILE, "\t.set\tnoat\n");					\
2903   fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n",	\
2904 	   reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]);	\
2905   fprintf (FILE,							\
2906 	   "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from  stack\n",	\
2907 	   TARGET_64BIT ? "dsubu" : "subu",				\
2908 	   reg_names[STACK_POINTER_REGNUM],				\
2909 	   reg_names[STACK_POINTER_REGNUM],				\
2910 	   Pmode == DImode ? 16 : 8);					\
2911   fprintf (FILE, "\tjal\t_mcount\n");                                   \
2912   fprintf (FILE, "\t.set\tat\n");					\
2913 }
2914 
2915 /* Define this macro if the code for function profiling should come
2916    before the function prologue.  Normally, the profiling code comes
2917    after.  */
2918 
2919 /* #define PROFILE_BEFORE_PROLOGUE */
2920 
2921 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2922    the stack pointer does not matter.  The value is tested only in
2923    functions that have frame pointers.
2924    No definition is equivalent to always zero.  */
2925 
2926 #define EXIT_IGNORE_STACK 1
2927 
2928 
2929 /* A C statement to output, on the stream FILE, assembler code for a
2930    block of data that contains the constant parts of a trampoline.
2931    This code should not include a label--the label is taken care of
2932    automatically.  */
2933 
2934 #define TRAMPOLINE_TEMPLATE(STREAM)					 \
2935 {									 \
2936   fprintf (STREAM, "\t.word\t0x03e00821\t\t# move   $1,$31\n");		\
2937   fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n");		\
2938   fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n");			\
2939   if (Pmode == DImode)							\
2940     {									\
2941       fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld     $3,20($31)\n");	\
2942       fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld     $2,28($31)\n");	\
2943     }									\
2944   else									\
2945     {									\
2946       fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw     $3,20($31)\n");	\
2947       fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw     $2,24($31)\n");	\
2948     }									\
2949   fprintf (STREAM, "\t.word\t0x0060c821\t\t# move   $25,$3 (abicalls)\n"); \
2950   fprintf (STREAM, "\t.word\t0x00600008\t\t# jr     $3\n");		\
2951   fprintf (STREAM, "\t.word\t0x0020f821\t\t# move   $31,$1\n");		\
2952   if (Pmode == DImode)							\
2953     {									\
2954       fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2955       fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2956     }									\
2957   else									\
2958     {									\
2959       fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2960       fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2961     }									\
2962 }
2963 
2964 /* A C expression for the size in bytes of the trampoline, as an
2965    integer.  */
2966 
2967 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2968 
2969 /* Alignment required for trampolines, in bits.  */
2970 
2971 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2972 
2973 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2974    program and data caches.  */
2975 
2976 #ifndef CACHE_FLUSH_FUNC
2977 #define CACHE_FLUSH_FUNC "_flush_cache"
2978 #endif
2979 
2980 /* A C statement to initialize the variable parts of a trampoline.
2981    ADDR is an RTX for the address of the trampoline; FNADDR is an
2982    RTX for the address of the nested function; STATIC_CHAIN is an
2983    RTX for the static chain value that should be passed to the
2984    function when it is called.  */
2985 
2986 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN)			    \
2987 {									    \
2988   rtx addr = ADDR;							    \
2989   if (Pmode == DImode)							    \
2990     {									    \
2991       emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2992       emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2993     }									    \
2994   else									    \
2995     {									    \
2996       emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2997       emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2998     }									    \
2999 									    \
3000   /* Flush both caches.  We need to flush the data cache in case	    \
3001      the system has a write-back cache.  */				    \
3002   /* ??? Should check the return value for errors.  */			    \
3003   if (mips_cache_flush_func && mips_cache_flush_func[0])		    \
3004     emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func),   \
3005 		       0, VOIDmode, 3, addr, Pmode,			    \
3006 		       GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
3007 		       GEN_INT (3), TYPE_MODE (integer_type_node));	    \
3008 }
3009 
3010 /* Addressing modes, and classification of registers for them.  */
3011 
3012 /* #define HAVE_POST_INCREMENT 0 */
3013 /* #define HAVE_POST_DECREMENT 0 */
3014 
3015 /* #define HAVE_PRE_DECREMENT 0 */
3016 /* #define HAVE_PRE_INCREMENT 0 */
3017 
3018 /* These assume that REGNO is a hard or pseudo reg number.
3019    They give nonzero only if REGNO is a hard reg of the suitable class
3020    or a pseudo reg currently allocated to a suitable hard reg.
3021    These definitions are NOT overridden anywhere.  */
3022 
3023 #define BASE_REG_P(regno, mode)					\
3024   (TARGET_MIPS16						\
3025    ? (M16_REG_P (regno)						\
3026       || (regno) == FRAME_POINTER_REGNUM			\
3027       || (regno) == ARG_POINTER_REGNUM				\
3028       || ((regno) == STACK_POINTER_REGNUM			\
3029 	  && (GET_MODE_SIZE (mode) == 4				\
3030 	      || GET_MODE_SIZE (mode) == 8)))			\
3031    : GP_REG_P (regno))
3032 
3033 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode)				    \
3034   BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
3035 	     (mode))
3036 
3037 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
3038   (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
3039 
3040 #define REGNO_OK_FOR_INDEX_P(regno)	0
3041 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
3042   GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
3043 
3044 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
3045    and check its validity for a certain class.
3046    We have two alternate definitions for each of them.
3047    The usual definition accepts all pseudo regs; the other rejects them all.
3048    The symbol REG_OK_STRICT causes the latter definition to be used.
3049 
3050    Most source files want to accept pseudo regs in the hope that
3051    they will get allocated to the class that the insn wants them to be in.
3052    Some source files that are used after register allocation
3053    need to be strict.  */
3054 
3055 #ifndef REG_OK_STRICT
3056 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3057   mips_reg_mode_ok_for_base_p (X, MODE, 0)
3058 #else
3059 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3060   mips_reg_mode_ok_for_base_p (X, MODE, 1)
3061 #endif
3062 
3063 #define REG_OK_FOR_INDEX_P(X) 0
3064 
3065 
3066 /* Maximum number of registers that can appear in a valid memory address.  */
3067 
3068 #define MAX_REGS_PER_ADDRESS 1
3069 
3070 /* A C compound statement with a conditional `goto LABEL;' executed
3071    if X (an RTX) is a legitimate memory address on the target
3072    machine for a memory operand of mode MODE.  */
3073 
3074 #if 1
3075 #define GO_PRINTF(x)	fprintf(stderr, (x))
3076 #define GO_PRINTF2(x,y)	fprintf(stderr, (x), (y))
3077 #define GO_DEBUG_RTX(x) debug_rtx(x)
3078 
3079 #else
3080 #define GO_PRINTF(x)
3081 #define GO_PRINTF2(x,y)
3082 #define GO_DEBUG_RTX(x)
3083 #endif
3084 
3085 #ifdef REG_OK_STRICT
3086 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)	\
3087 {						\
3088   if (mips_legitimate_address_p (MODE, X, 1))	\
3089     goto ADDR;					\
3090 }
3091 #else
3092 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)	\
3093 {						\
3094   if (mips_legitimate_address_p (MODE, X, 0))	\
3095     goto ADDR;					\
3096 }
3097 #endif
3098 
3099 /* A C expression that is 1 if the RTX X is a constant which is a
3100    valid address.  This is defined to be the same as `CONSTANT_P (X)',
3101    but rejecting CONST_DOUBLE.  */
3102 /* When pic, we must reject addresses of the form symbol+large int.
3103    This is because an instruction `sw $4,s+70000' needs to be converted
3104    by the assembler to `lw $at,s($gp);sw $4,70000($at)'.  Normally the
3105    assembler would use $at as a temp to load in the large offset.  In this
3106    case $at is already in use.  We convert such problem addresses to
3107    `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS.  */
3108 /* ??? SGI IRIX 6 N32/N64 assembler fails for CONST address, so reject them
3109    when !TARGET_GAS or ABI_32.  */
3110 /* We should be rejecting everything but const addresses.  */
3111 #define CONSTANT_ADDRESS_P(X)						\
3112   (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
3113     || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH		\
3114     || (GET_CODE (X) == CONST						\
3115 	&& ! (flag_pic && pic_address_needs_scratch (X))		\
3116 	&& (TARGET_GAS || mips_abi == ABI_32)))
3117 
3118 
3119 /* Define this, so that when PIC, reload won't try to reload invalid
3120    addresses which require two reload registers.  */
3121 
3122 #define LEGITIMATE_PIC_OPERAND_P(X)  (! pic_address_needs_scratch (X))
3123 
3124 /* Nonzero if the constant value X is a legitimate general operand.
3125    It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3126 
3127    At present, GAS doesn't understand li.[sd], so don't allow it
3128    to be generated at present.  Also, the MIPS assembler does not
3129    grok li.d Infinity.  */
3130 
3131 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3132    Note that the Irix 6 assembler problem may already be fixed.
3133    Note also that the GET_CODE (X) == CONST test catches the mips16
3134    gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3135    a LEGITIMATE_CONSTANT.  If we ever want mips16 and ABI_N32 or
3136    ABI_64 to work together, we'll need to fix this.  */
3137 #define LEGITIMATE_CONSTANT_P(X)					\
3138   ((GET_CODE (X) != CONST_DOUBLE					\
3139     || mips_const_double_ok (X, GET_MODE (X)))				\
3140    && ! (GET_CODE (X) == CONST 						\
3141 	 && ! TARGET_GAS						\
3142 	 && (mips_abi == ABI_N32 					\
3143 	     || mips_abi == ABI_64))					\
3144    && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
3145 
3146 /* A C compound statement that attempts to replace X with a valid
3147    memory address for an operand of mode MODE.  WIN will be a C
3148    statement label elsewhere in the code; the macro definition may
3149    use
3150 
3151           GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3152 
3153    to avoid further processing if the address has become legitimate.
3154 
3155    X will always be the result of a call to `break_out_memory_refs',
3156    and OLDX will be the operand that was given to that function to
3157    produce X.
3158 
3159    The code generated by this macro should not alter the
3160    substructure of X.  If it transforms X into a more legitimate
3161    form, it should assign X (which will always be a C variable) a
3162    new value.
3163 
3164    It is not necessary for this macro to come up with a legitimate
3165    address.  The compiler has standard ways of doing so in all
3166    cases.  In fact, it is safe for this macro to do nothing.  But
3167    often a machine-dependent strategy can generate better code.
3168 
3169    For the MIPS, transform:
3170 
3171 	memory(X + <large int>)
3172 
3173    into:
3174 
3175 	Y = <large int> & ~0x7fff;
3176 	Z = X + Y
3177 	memory (Z + (<large int> & 0x7fff));
3178 
3179    This is for CSE to find several similar references, and only use one Z.
3180 
3181    When PIC, convert addresses of the form memory (symbol+large int) to
3182    memory (reg+large int).  */
3183 
3184 
3185 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)				\
3186 {									\
3187   register rtx xinsn = (X);						\
3188 									\
3189   if (TARGET_DEBUG_B_MODE)						\
3190     {									\
3191       GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n");			\
3192       GO_DEBUG_RTX (xinsn);						\
3193     }									\
3194 									\
3195   if (mips_split_addresses && mips_check_split (X, MODE))		\
3196     {									\
3197       /* ??? Is this ever executed?  */					\
3198       X = gen_rtx_LO_SUM (Pmode,					\
3199 			  copy_to_mode_reg (Pmode,			\
3200 					    gen_rtx (HIGH, Pmode, X)),	\
3201 			  X);						\
3202       goto WIN;								\
3203     }									\
3204 									\
3205   if (GET_CODE (xinsn) == CONST						\
3206       && ((flag_pic && pic_address_needs_scratch (xinsn))		\
3207 	  /* ??? SGI's Irix 6 assembler can't handle CONST.  */		\
3208 	  || (!TARGET_GAS						\
3209 	      && (mips_abi == ABI_N32 					\
3210 	          || mips_abi == ABI_64))))    				\
3211     {									\
3212       rtx ptr_reg = gen_reg_rtx (Pmode);				\
3213       rtx constant = XEXP (XEXP (xinsn, 0), 1);				\
3214 									\
3215       emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0));		\
3216 									\
3217       X = gen_rtx_PLUS (Pmode, ptr_reg, constant);			\
3218       if (SMALL_INT (constant))						\
3219 	goto WIN;							\
3220       /* Otherwise we fall through so the code below will fix the	\
3221 	 constant.  */							\
3222       xinsn = X;							\
3223     }									\
3224 									\
3225   if (GET_CODE (xinsn) == PLUS)						\
3226     {									\
3227       register rtx xplus0 = XEXP (xinsn, 0);				\
3228       register rtx xplus1 = XEXP (xinsn, 1);				\
3229       register enum rtx_code code0 = GET_CODE (xplus0);			\
3230       register enum rtx_code code1 = GET_CODE (xplus1);			\
3231 									\
3232       if (code0 != REG && code1 == REG)					\
3233 	{								\
3234 	  xplus0 = XEXP (xinsn, 1);					\
3235 	  xplus1 = XEXP (xinsn, 0);					\
3236 	  code0 = GET_CODE (xplus0);					\
3237 	  code1 = GET_CODE (xplus1);					\
3238 	}								\
3239 									\
3240       if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)		\
3241 	  && code1 == CONST_INT && !SMALL_INT (xplus1))			\
3242 	{								\
3243 	  rtx int_reg = gen_reg_rtx (Pmode);				\
3244 	  rtx ptr_reg = gen_reg_rtx (Pmode);				\
3245 									\
3246 	  emit_move_insn (int_reg,					\
3247 			  GEN_INT (INTVAL (xplus1) & ~ 0x7fff));	\
3248 									\
3249 	  emit_insn (gen_rtx_SET (VOIDmode,				\
3250 				  ptr_reg,				\
3251 				  gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3252 									\
3253 	  X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff);	\
3254 	  goto WIN;							\
3255 	}								\
3256     }									\
3257 									\
3258   if (TARGET_DEBUG_B_MODE)						\
3259     GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n");			\
3260 }
3261 
3262 
3263 /* A C statement or compound statement with a conditional `goto
3264    LABEL;' executed if memory address X (an RTX) can have different
3265    meanings depending on the machine mode of the memory reference it
3266    is used for.
3267 
3268    Autoincrement and autodecrement addresses typically have
3269    mode-dependent effects because the amount of the increment or
3270    decrement is the size of the operand being addressed.  Some
3271    machines have other mode-dependent addresses.  Many RISC machines
3272    have no mode-dependent addresses.
3273 
3274    You may assume that ADDR is a valid address for the machine.  */
3275 
3276 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3277 
3278 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3279    'the start of the function that this code is output in'.  */
3280 
3281 #define ASM_OUTPUT_LABELREF(FILE,NAME)  \
3282   if (strcmp (NAME, "..CURRENT_FUNCTION") == 0)				\
3283     asm_fprintf ((FILE), "%U%s",					\
3284 		 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));	\
3285   else									\
3286     asm_fprintf ((FILE), "%U%s", (NAME))
3287 
3288 /* The mips16 wants the constant pool to be after the function,
3289    because the PC relative load instructions use unsigned offsets.  */
3290 
3291 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3292 
3293 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE)	\
3294   mips_string_length = 0;
3295 
3296 #if 0
3297 /* In mips16 mode, put most string constants after the function.  */
3298 #define CONSTANT_AFTER_FUNCTION_P(tree)				\
3299   (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3300 #endif
3301 
3302 /* Specify the machine mode that this machine uses
3303    for the index in the tablejump instruction.
3304    ??? Using HImode in mips16 mode can cause overflow.  However, the
3305    overflow is no more likely than the overflow in a branch
3306    instruction.  Large functions can currently break in both ways.  */
3307 #define CASE_VECTOR_MODE \
3308   (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3309 
3310 /* Define as C expression which evaluates to nonzero if the tablejump
3311    instruction expects the table to contain offsets from the address of the
3312    table.
3313    Do not define this if the table should contain absolute addresses.  */
3314 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3315 
3316 /* Define this as 1 if `char' should by default be signed; else as 0.  */
3317 #ifndef DEFAULT_SIGNED_CHAR
3318 #define DEFAULT_SIGNED_CHAR 1
3319 #endif
3320 
3321 /* Max number of bytes we can move from memory to memory
3322    in one reasonably fast instruction.  */
3323 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3324 #define MAX_MOVE_MAX 8
3325 
3326 /* Define this macro as a C expression which is nonzero if
3327    accessing less than a word of memory (i.e. a `char' or a
3328    `short') is no faster than accessing a word of memory, i.e., if
3329    such access require more than one instruction or if there is no
3330    difference in cost between byte and (aligned) word loads.
3331 
3332    On RISC machines, it tends to generate better code to define
3333    this as 1, since it avoids making a QI or HI mode register.  */
3334 #define SLOW_BYTE_ACCESS 1
3335 
3336 /* We assume that the store-condition-codes instructions store 0 for false
3337    and some other value for true.  This is the value stored for true.  */
3338 
3339 #define STORE_FLAG_VALUE 1
3340 
3341 /* Define this to be nonzero if shift instructions ignore all but the low-order
3342    few bits.  */
3343 #define SHIFT_COUNT_TRUNCATED 1
3344 
3345 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3346    is done just by pretending it is already truncated.  */
3347 /* In 64 bit mode, 32 bit instructions require that register values be properly
3348    sign-extended to 64 bits.  As a result, a truncate is not a no-op if it
3349    converts a value >32 bits to a value <32 bits.  */
3350 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3351    Something needs to be done about this.  Perhaps not use any 32 bit
3352    instructions?  Perhaps use PROMOTE_MODE?  */
3353 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3354   (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3355 
3356 /* Specify the machine mode that pointers have.
3357    After generation of rtl, the compiler makes no further distinction
3358    between pointers and any other objects of this machine mode.
3359 
3360    For MIPS we make pointers are the smaller of longs and gp-registers.  */
3361 
3362 #ifndef Pmode
3363 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3364 #endif
3365 
3366 /* A function address in a call instruction
3367    is a word address (for indexing purposes)
3368    so give the MEM rtx a words's mode.  */
3369 
3370 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3371 
3372 
3373 /* A part of a C `switch' statement that describes the relative
3374    costs of constant RTL expressions.  It must contain `case'
3375    labels for expression codes `const_int', `const', `symbol_ref',
3376    `label_ref' and `const_double'.  Each case must ultimately reach
3377    a `return' statement to return the relative cost of the use of
3378    that kind of constant value in an expression.  The cost may
3379    depend on the precise value of the constant, which is available
3380    for examination in X.
3381 
3382    CODE is the expression code--redundant, since it can be obtained
3383    with `GET_CODE (X)'.  */
3384 
3385 #define CONST_COSTS(X,CODE,OUTER_CODE)					\
3386   case CONST_INT:							\
3387     if (! TARGET_MIPS16)						\
3388       {									\
3389 	/* Always return 0, since we don't have different sized		\
3390 	   instructions, hence different costs according to Richard	\
3391 	   Kenner */							\
3392 	return 0;							\
3393       }									\
3394     if ((OUTER_CODE) == SET)						\
3395       {									\
3396 	if (INTVAL (X) >= 0 && INTVAL (X) < 0x100)			\
3397 	  return 0;							\
3398 	else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000)		\
3399 		 || (INTVAL (X) < 0 && INTVAL (X) > -0x100))		\
3400 	  return COSTS_N_INSNS (1);					\
3401 	else								\
3402 	  return COSTS_N_INSNS (2);					\
3403       }									\
3404     /* A PLUS could be an address.  We don't want to force an address	\
3405        to use a register, so accept any signed 16 bit value without	\
3406        complaint.  */							\
3407     if ((OUTER_CODE) == PLUS						\
3408 	&& INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000)		\
3409       return 0;								\
3410     /* A number between 1 and 8 inclusive is efficient for a shift.	\
3411        Otherwise, we will need an extended instruction.  */		\
3412     if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT		\
3413 	|| (OUTER_CODE) == LSHIFTRT)					\
3414       {									\
3415 	if (INTVAL (X) >= 1 && INTVAL (X) <= 8)				\
3416 	  return 0;							\
3417 	return COSTS_N_INSNS (1);					\
3418       }									\
3419     /* We can use cmpi for an xor with an unsigned 16 bit value.  */	\
3420     if ((OUTER_CODE) == XOR						\
3421 	&& INTVAL (X) >= 0 && INTVAL (X) < 0x10000)			\
3422       return 0;								\
3423     /* We may be able to use slt or sltu for a comparison with a	\
3424        signed 16 bit value.  (The boundary conditions aren't quite	\
3425        right, but this is just a heuristic anyhow.)  */			\
3426     if (((OUTER_CODE) == LT || (OUTER_CODE) == LE			\
3427 	 || (OUTER_CODE) == GE || (OUTER_CODE) == GT			\
3428 	 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU			\
3429 	 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU)			\
3430 	&& INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000)		\
3431       return 0;								\
3432     /* Equality comparisons with 0 are cheap.  */			\
3433     if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE)			\
3434 	&& INTVAL (X) == 0)						\
3435       return 0;								\
3436 									\
3437     /* Otherwise, work out the cost to load the value into a		\
3438        register.  */							\
3439     if (INTVAL (X) >= 0 && INTVAL (X) < 0x100)				\
3440       return COSTS_N_INSNS (1);						\
3441     else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000)			\
3442 	     || (INTVAL (X) < 0 && INTVAL (X) > -0x100))		\
3443       return COSTS_N_INSNS (2);						\
3444     else								\
3445       return COSTS_N_INSNS (3);						\
3446 									\
3447   case LABEL_REF:							\
3448     return COSTS_N_INSNS (2);						\
3449 									\
3450   case CONST:								\
3451     {									\
3452       rtx offset = const0_rtx;						\
3453       rtx symref = eliminate_constant_term (XEXP (X, 0), &offset);	\
3454 									\
3455       if (TARGET_MIPS16 && mips16_gp_offset_p (X))			\
3456 	{								\
3457 	  /* Treat this like a signed 16 bit CONST_INT.  */		\
3458 	  if ((OUTER_CODE) == PLUS)					\
3459 	    return 0;							\
3460 	  else if ((OUTER_CODE) == SET)					\
3461 	    return COSTS_N_INSNS (1);					\
3462 	  else								\
3463 	    return COSTS_N_INSNS (2);					\
3464 	}								\
3465 									\
3466       if (GET_CODE (symref) == LABEL_REF)				\
3467 	return COSTS_N_INSNS (2);					\
3468 									\
3469       if (GET_CODE (symref) != SYMBOL_REF)				\
3470 	return COSTS_N_INSNS (4);					\
3471 									\
3472       /* let's be paranoid....  */					\
3473       if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767)		\
3474 	return COSTS_N_INSNS (2);					\
3475 									\
3476       return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2);		\
3477     }									\
3478 									\
3479   case SYMBOL_REF:							\
3480     return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2);			\
3481 									\
3482   case CONST_DOUBLE:							\
3483     {									\
3484       rtx high, low;							\
3485       if (TARGET_MIPS16)						\
3486 	return COSTS_N_INSNS (4);					\
3487       split_double (X, &high, &low);					\
3488       return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high))	\
3489 			     || low == CONST0_RTX (GET_MODE (low)))	\
3490 			    ? 2 : 4);					\
3491     }
3492 
3493 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3494    This can be used, for example, to indicate how costly a multiply
3495    instruction is.  In writing this macro, you can use the construct
3496    `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3497 
3498    This macro is optional; do not define it if the default cost
3499    assumptions are adequate for the target machine.
3500 
3501    If -mdebugd is used, change the multiply cost to 2, so multiply by
3502    a constant isn't converted to a series of shifts.  This helps
3503    strength reduction, and also makes it easier to identify what the
3504    compiler is doing.  */
3505 
3506 /* ??? Fix this to be right for the R8000.  */
3507 #define RTX_COSTS(X,CODE,OUTER_CODE)					\
3508   case MEM:								\
3509     {									\
3510       int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3511       if (simple_memory_operand (X, GET_MODE (X)))			\
3512 	return COSTS_N_INSNS (num_words);				\
3513 									\
3514       return COSTS_N_INSNS (2*num_words);				\
3515     }									\
3516 									\
3517   case FFS:								\
3518     return COSTS_N_INSNS (6);						\
3519 									\
3520   case NOT:								\
3521     return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3522 									\
3523   case AND:								\
3524   case IOR:								\
3525   case XOR:								\
3526     if (GET_MODE (X) == DImode && !TARGET_64BIT)			\
3527       return COSTS_N_INSNS (2);						\
3528 									\
3529     break;								\
3530 									\
3531   case ASHIFT:								\
3532   case ASHIFTRT:							\
3533   case LSHIFTRT:							\
3534     if (GET_MODE (X) == DImode && !TARGET_64BIT)			\
3535       return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3536 									\
3537     break;								\
3538 									\
3539   case ABS:								\
3540     {									\
3541       enum machine_mode xmode = GET_MODE (X);				\
3542       if (xmode == SFmode || xmode == DFmode)				\
3543 	return COSTS_N_INSNS (1);					\
3544 									\
3545       return COSTS_N_INSNS (4);						\
3546     }									\
3547 									\
3548   case PLUS:								\
3549   case MINUS:								\
3550     {									\
3551       enum machine_mode xmode = GET_MODE (X);				\
3552       if (xmode == SFmode || xmode == DFmode)				\
3553 	{								\
3554 	  if (TUNE_MIPS3000                                             \
3555               || TUNE_MIPS3900)         				\
3556 	    return COSTS_N_INSNS (2);					\
3557 	  else if (TUNE_MIPS6000)       				\
3558 	    return COSTS_N_INSNS (3);					\
3559 	  else								\
3560 	    return COSTS_N_INSNS (6);					\
3561 	}								\
3562 									\
3563       if (xmode == DImode && !TARGET_64BIT)				\
3564 	return COSTS_N_INSNS (4);					\
3565 									\
3566       break;								\
3567     }									\
3568 									\
3569   case NEG:								\
3570     if (GET_MODE (X) == DImode && !TARGET_64BIT)			\
3571       return 4;								\
3572 									\
3573     break;								\
3574 									\
3575   case MULT:								\
3576     {									\
3577       enum machine_mode xmode = GET_MODE (X);				\
3578       if (xmode == SFmode)						\
3579 	{								\
3580 	  if (TUNE_MIPS3000						\
3581 	      || TUNE_MIPS3900						\
3582 	      || TUNE_MIPS5000)						\
3583 	    return COSTS_N_INSNS (4);					\
3584 	  else if (TUNE_MIPS6000                                        \
3585 		   || TUNE_MIPS5400                                     \
3586 		   || TUNE_MIPS5500)					\
3587 	    return COSTS_N_INSNS (5);					\
3588 	  else								\
3589 	    return COSTS_N_INSNS (7);					\
3590 	}								\
3591 									\
3592       if (xmode == DFmode)						\
3593 	{								\
3594 	  if (TUNE_MIPS3000						\
3595 	      || TUNE_MIPS3900						\
3596 	      || TUNE_MIPS5000)						\
3597 	    return COSTS_N_INSNS (5);					\
3598 	  else if (TUNE_MIPS6000                                        \
3599 		   || TUNE_MIPS5400                                     \
3600 		   || TUNE_MIPS5500)					\
3601 	    return COSTS_N_INSNS (6);					\
3602 	  else								\
3603 	    return COSTS_N_INSNS (8);					\
3604 	}								\
3605 									\
3606       if (TUNE_MIPS3000)						\
3607 	return COSTS_N_INSNS (12);					\
3608       else if (TUNE_MIPS3900)						\
3609 	return COSTS_N_INSNS (2);					\
3610      else if (TUNE_MIPS5400 || TUNE_MIPS5500)                           \
3611         return COSTS_N_INSNS ((xmode == DImode) ? 4 : 3);               \
3612       else if (TUNE_MIPS6000)						\
3613 	return COSTS_N_INSNS (17);					\
3614       else if (TUNE_MIPS5000)						\
3615 	return COSTS_N_INSNS (5);					\
3616       else								\
3617 	return COSTS_N_INSNS (10);					\
3618     }									\
3619 									\
3620   case DIV:								\
3621   case MOD:								\
3622     {									\
3623       enum machine_mode xmode = GET_MODE (X);				\
3624       if (xmode == SFmode)						\
3625 	{								\
3626 	  if (TUNE_MIPS3000						\
3627               || TUNE_MIPS3900)						\
3628 	    return COSTS_N_INSNS (12);					\
3629 	  else if (TUNE_MIPS6000)					\
3630 	    return COSTS_N_INSNS (15);					\
3631          else if (TUNE_MIPS5400 || TUNE_MIPS5500)                       \
3632             return COSTS_N_INSNS (30);                                  \
3633 	  else								\
3634 	    return COSTS_N_INSNS (23);					\
3635 	}								\
3636 									\
3637       if (xmode == DFmode)						\
3638 	{								\
3639 	  if (TUNE_MIPS3000						\
3640               || TUNE_MIPS3900)						\
3641 	    return COSTS_N_INSNS (19);					\
3642           else if (TUNE_MIPS5400 || TUNE_MIPS5500)                      \
3643             return COSTS_N_INSNS (59);                                  \
3644 	  else if (TUNE_MIPS6000)					\
3645 	    return COSTS_N_INSNS (16);					\
3646 	  else								\
3647 	    return COSTS_N_INSNS (36);					\
3648 	}								\
3649     }									\
3650     /* fall through */							\
3651 									\
3652   case UDIV:								\
3653   case UMOD:								\
3654     if (TUNE_MIPS3000							\
3655         || TUNE_MIPS3900)						\
3656       return COSTS_N_INSNS (35);					\
3657     else if (TUNE_MIPS6000)						\
3658       return COSTS_N_INSNS (38);					\
3659     else if (TUNE_MIPS5000)						\
3660       return COSTS_N_INSNS (36);					\
3661     else if (TUNE_MIPS5400 || TUNE_MIPS5500)                            \
3662       return COSTS_N_INSNS ((GET_MODE (X) == SImode) ? 42 : 74);        \
3663     else								\
3664       return COSTS_N_INSNS (69);					\
3665 									\
3666   case SIGN_EXTEND:							\
3667     /* A sign extend from SImode to DImode in 64 bit mode is often	\
3668        zero instructions, because the result can often be used		\
3669        directly by another instruction; we'll call it one.  */		\
3670     if (TARGET_64BIT && GET_MODE (X) == DImode				\
3671 	&& GET_MODE (XEXP (X, 0)) == SImode)				\
3672       return COSTS_N_INSNS (1);						\
3673     else								\
3674       return COSTS_N_INSNS (2);						\
3675 									\
3676   case ZERO_EXTEND:							\
3677     if (TARGET_64BIT && GET_MODE (X) == DImode				\
3678 	&& GET_MODE (XEXP (X, 0)) == SImode)				\
3679       return COSTS_N_INSNS (2);						\
3680     else								\
3681       return COSTS_N_INSNS (1);
3682 
3683 /* An expression giving the cost of an addressing mode that
3684    contains ADDRESS.  If not defined, the cost is computed from the
3685    form of the ADDRESS expression and the `CONST_COSTS' values.
3686 
3687    For most CISC machines, the default cost is a good approximation
3688    of the true cost of the addressing mode.  However, on RISC
3689    machines, all instructions normally have the same length and
3690    execution time.  Hence all addresses will have equal costs.
3691 
3692    In cases where more than one form of an address is known, the
3693    form with the lowest cost will be used.  If multiple forms have
3694    the same, lowest, cost, the one that is the most complex will be
3695    used.
3696 
3697    For example, suppose an address that is equal to the sum of a
3698    register and a constant is used twice in the same basic block.
3699    When this macro is not defined, the address will be computed in
3700    a register and memory references will be indirect through that
3701    register.  On machines where the cost of the addressing mode
3702    containing the sum is no higher than that of a simple indirect
3703    reference, this will produce an additional instruction and
3704    possibly require an additional register.  Proper specification
3705    of this macro eliminates this overhead for such machines.
3706 
3707    Similar use of this macro is made in strength reduction of loops.
3708 
3709    ADDRESS need not be valid as an address.  In such a case, the
3710    cost is not relevant and can be any value; invalid addresses
3711    need not be assigned a different cost.
3712 
3713    On machines where an address involving more than one register is
3714    as cheap as an address computation involving only one register,
3715    defining `ADDRESS_COST' to reflect this can cause two registers
3716    to be live over a region of code where only one would have been
3717    if `ADDRESS_COST' were not defined in that manner.  This effect
3718    should be considered in the definition of this macro.
3719    Equivalent costs should probably only be given to addresses with
3720    different numbers of registers on machines with lots of registers.
3721 
3722    This macro will normally either not be defined or be defined as
3723    a constant.  */
3724 
3725 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3726 
3727 /* A C expression for the cost of moving data from a register in
3728    class FROM to one in class TO.  The classes are expressed using
3729    the enumeration values such as `GENERAL_REGS'.  A value of 2 is
3730    the default; other values are interpreted relative to that.
3731 
3732    It is not required that the cost always equal 2 when FROM is the
3733    same as TO; on some machines it is expensive to move between
3734    registers if they are not general registers.
3735 
3736    If reload sees an insn consisting of a single `set' between two
3737    hard registers, and if `REGISTER_MOVE_COST' applied to their
3738    classes returns a value of 2, reload does not check to ensure
3739    that the constraints of the insn are met.  Setting a cost of
3740    other than 2 will allow reload to verify that the constraints are
3741    met.  You should do this if the `movM' pattern's constraints do
3742    not allow such copying. */
3743 
3744 #define REGISTER_MOVE_COST(MODE, FROM, TO)				\
3745   mips_register_move_cost (MODE, FROM, TO)
3746 
3747 /* ??? Fix this to be right for the R8000.  */
3748 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3749   (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3750    + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3751 
3752 /* Define if copies to/from condition code registers should be avoided.
3753 
3754    This is needed for the MIPS because reload_outcc is not complete;
3755    it needs to handle cases where the source is a general or another
3756    condition code register.  */
3757 #define AVOID_CCMODE_COPIES
3758 
3759 /* A C expression for the cost of a branch instruction.  A value of
3760    1 is the default; other values are interpreted relative to that.  */
3761 
3762 /* ??? Fix this to be right for the R8000.  */
3763 #define BRANCH_COST							\
3764   ((! TARGET_MIPS16							\
3765     && (TUNE_MIPS4000 || TUNE_MIPS6000))	\
3766    ? 2 : 1)
3767 
3768 /* If defined, modifies the length assigned to instruction INSN as a
3769    function of the context in which it is used.  LENGTH is an lvalue
3770    that contains the initially computed length of the insn and should
3771    be updated with the correct length of the insn.  */
3772 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3773   ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3774 
3775 
3776 /* Optionally define this if you have added predicates to
3777    `MACHINE.c'.  This macro is called within an initializer of an
3778    array of structures.  The first field in the structure is the
3779    name of a predicate and the second field is an array of rtl
3780    codes.  For each predicate, list all rtl codes that can be in
3781    expressions matched by the predicate.  The list should have a
3782    trailing comma.  Here is an example of two entries in the list
3783    for a typical RISC machine:
3784 
3785    #define PREDICATE_CODES \
3786      {"gen_reg_rtx_operand", {SUBREG, REG}},  \
3787      {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3788 
3789    Defining this macro does not affect the generated code (however,
3790    incorrect definitions that omit an rtl code that may be matched
3791    by the predicate can cause the compiler to malfunction).
3792    Instead, it allows the table built by `genrecog' to be more
3793    compact and efficient, thus speeding up the compiler.  The most
3794    important predicates to include in the list specified by this
3795    macro are thoses used in the most insn patterns.  */
3796 
3797 #define PREDICATE_CODES							\
3798   {"uns_arith_operand",		{ REG, CONST_INT, SUBREG }},		\
3799   {"arith_operand",		{ REG, CONST_INT, SUBREG }},		\
3800   {"arith32_operand",		{ REG, CONST_INT, SUBREG }},		\
3801   {"reg_or_0_operand",		{ REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3802   {"true_reg_or_0_operand",	{ REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3803   {"small_int",			{ CONST_INT }},				\
3804   {"large_int",			{ CONST_INT }},				\
3805   {"mips_const_double_ok",	{ CONST_DOUBLE }},			\
3806   {"const_float_1_operand",	{ CONST_DOUBLE }},			\
3807   {"simple_memory_operand",	{ MEM, SUBREG }},			\
3808   {"equality_op",		{ EQ, NE }},				\
3809   {"cmp_op",			{ EQ, NE, GT, GE, GTU, GEU, LT, LE,	\
3810 				  LTU, LEU }},				\
3811   {"trap_cmp_op",		{ EQ, NE, GE, GEU, LT, LTU }},		\
3812   {"pc_or_label_operand",	{ PC, LABEL_REF }},			\
3813   {"call_insn_operand",		{ CONST_INT, CONST, SYMBOL_REF, REG}},	\
3814   {"move_operand", 		{ CONST_INT, CONST_DOUBLE, CONST,	\
3815 				  SYMBOL_REF, LABEL_REF, SUBREG,	\
3816 				  REG, MEM}},				\
3817   {"movdi_operand",		{ CONST_INT, CONST_DOUBLE, CONST,	\
3818 				  SYMBOL_REF, LABEL_REF, SUBREG, REG,	\
3819 				  MEM, SIGN_EXTEND }},			\
3820   {"se_register_operand",	{ SUBREG, REG, SIGN_EXTEND }},		\
3821   {"se_reg_or_0_operand",	{ REG, CONST_INT, CONST_DOUBLE, SUBREG,	\
3822 				  SIGN_EXTEND }},			\
3823   {"se_uns_arith_operand",	{ REG, CONST_INT, SUBREG,		\
3824 				  SIGN_EXTEND }},			\
3825   {"se_arith_operand",		{ REG, CONST_INT, SUBREG,		\
3826 				  SIGN_EXTEND }},			\
3827   {"se_nonmemory_operand",	{ CONST_INT, CONST_DOUBLE, CONST,	\
3828 				  SYMBOL_REF, LABEL_REF, SUBREG,	\
3829 				  REG, SIGN_EXTEND }},			\
3830   {"consttable_operand",	{ LABEL_REF, SYMBOL_REF, CONST_INT,	\
3831 				  CONST_DOUBLE, CONST }},		\
3832   {"fcc_register_operand",	{ REG, SUBREG }},			\
3833   {"extend_operator",           { SIGN_EXTEND, ZERO_EXTEND }},          \
3834   {"highpart_shift_operator",   { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3835 
3836 /* A list of predicates that do special things with modes, and so
3837    should not elicit warnings for VOIDmode match_operand.  */
3838 
3839 #define SPECIAL_MODE_PREDICATES \
3840   "pc_or_label_operand",
3841 
3842 
3843 /* If defined, a C statement to be executed just prior to the
3844    output of assembler code for INSN, to modify the extracted
3845    operands so they will be output differently.
3846 
3847    Here the argument OPVEC is the vector containing the operands
3848    extracted from INSN, and NOPERANDS is the number of elements of
3849    the vector which contain meaningful data for this insn.  The
3850    contents of this vector are what will be used to convert the
3851    insn template into assembler code, so you can change the
3852    assembler output by changing the contents of the vector.
3853 
3854    We use it to check if the current insn needs a nop in front of it
3855    because of load delays, and also to update the delay slot
3856    statistics.  */
3857 
3858 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)			\
3859   final_prescan_insn (INSN, OPVEC, NOPERANDS)
3860 
3861 
3862 /* Control the assembler format that we output.  */
3863 
3864 /* Output at beginning of assembler file.
3865    If we are optimizing to use the global pointer, create a temporary
3866    file to hold all of the text stuff, and write it out to the end.
3867    This is needed because the MIPS assembler is evidently one pass,
3868    and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3869    declaration when the code is processed, it generates a two
3870    instruction sequence.  */
3871 
3872 #undef ASM_FILE_START
3873 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3874 
3875 /* Output to assembler file text saying following lines
3876    may contain character constants, extra white space, comments, etc.  */
3877 
3878 #ifndef ASM_APP_ON
3879 #define ASM_APP_ON " #APP\n"
3880 #endif
3881 
3882 /* Output to assembler file text saying following lines
3883    no longer contain unusual constructs.  */
3884 
3885 #ifndef ASM_APP_OFF
3886 #define ASM_APP_OFF " #NO_APP\n"
3887 #endif
3888 
3889 /* How to refer to registers in assembler output.
3890    This sequence is indexed by compiler's hard-register-number (see above).
3891 
3892    In order to support the two different conventions for register names,
3893    we use the name of a table set up in mips.c, which is overwritten
3894    if -mrnames is used.  */
3895 
3896 #define REGISTER_NAMES							\
3897 {									\
3898   &mips_reg_names[ 0][0],						\
3899   &mips_reg_names[ 1][0],						\
3900   &mips_reg_names[ 2][0],						\
3901   &mips_reg_names[ 3][0],						\
3902   &mips_reg_names[ 4][0],						\
3903   &mips_reg_names[ 5][0],						\
3904   &mips_reg_names[ 6][0],						\
3905   &mips_reg_names[ 7][0],						\
3906   &mips_reg_names[ 8][0],						\
3907   &mips_reg_names[ 9][0],						\
3908   &mips_reg_names[10][0],						\
3909   &mips_reg_names[11][0],						\
3910   &mips_reg_names[12][0],						\
3911   &mips_reg_names[13][0],						\
3912   &mips_reg_names[14][0],						\
3913   &mips_reg_names[15][0],						\
3914   &mips_reg_names[16][0],						\
3915   &mips_reg_names[17][0],						\
3916   &mips_reg_names[18][0],						\
3917   &mips_reg_names[19][0],						\
3918   &mips_reg_names[20][0],						\
3919   &mips_reg_names[21][0],						\
3920   &mips_reg_names[22][0],						\
3921   &mips_reg_names[23][0],						\
3922   &mips_reg_names[24][0],						\
3923   &mips_reg_names[25][0],						\
3924   &mips_reg_names[26][0],						\
3925   &mips_reg_names[27][0],						\
3926   &mips_reg_names[28][0],						\
3927   &mips_reg_names[29][0],						\
3928   &mips_reg_names[30][0],						\
3929   &mips_reg_names[31][0],						\
3930   &mips_reg_names[32][0],						\
3931   &mips_reg_names[33][0],						\
3932   &mips_reg_names[34][0],						\
3933   &mips_reg_names[35][0],						\
3934   &mips_reg_names[36][0],						\
3935   &mips_reg_names[37][0],						\
3936   &mips_reg_names[38][0],						\
3937   &mips_reg_names[39][0],						\
3938   &mips_reg_names[40][0],						\
3939   &mips_reg_names[41][0],						\
3940   &mips_reg_names[42][0],						\
3941   &mips_reg_names[43][0],						\
3942   &mips_reg_names[44][0],						\
3943   &mips_reg_names[45][0],						\
3944   &mips_reg_names[46][0],						\
3945   &mips_reg_names[47][0],						\
3946   &mips_reg_names[48][0],						\
3947   &mips_reg_names[49][0],						\
3948   &mips_reg_names[50][0],						\
3949   &mips_reg_names[51][0],						\
3950   &mips_reg_names[52][0],						\
3951   &mips_reg_names[53][0],						\
3952   &mips_reg_names[54][0],						\
3953   &mips_reg_names[55][0],						\
3954   &mips_reg_names[56][0],						\
3955   &mips_reg_names[57][0],						\
3956   &mips_reg_names[58][0],						\
3957   &mips_reg_names[59][0],						\
3958   &mips_reg_names[60][0],						\
3959   &mips_reg_names[61][0],						\
3960   &mips_reg_names[62][0],						\
3961   &mips_reg_names[63][0],						\
3962   &mips_reg_names[64][0],						\
3963   &mips_reg_names[65][0],						\
3964   &mips_reg_names[66][0],						\
3965   &mips_reg_names[67][0],						\
3966   &mips_reg_names[68][0],						\
3967   &mips_reg_names[69][0],						\
3968   &mips_reg_names[70][0],						\
3969   &mips_reg_names[71][0],						\
3970   &mips_reg_names[72][0],						\
3971   &mips_reg_names[73][0],						\
3972   &mips_reg_names[74][0],						\
3973   &mips_reg_names[75][0],						\
3974   &mips_reg_names[76][0],						\
3975   &mips_reg_names[77][0],						\
3976   &mips_reg_names[78][0],						\
3977   &mips_reg_names[79][0],						\
3978   &mips_reg_names[80][0],						\
3979   &mips_reg_names[81][0],						\
3980   &mips_reg_names[82][0],						\
3981   &mips_reg_names[83][0],						\
3982   &mips_reg_names[84][0],						\
3983   &mips_reg_names[85][0],						\
3984   &mips_reg_names[86][0],						\
3985   &mips_reg_names[87][0],						\
3986   &mips_reg_names[88][0],						\
3987   &mips_reg_names[89][0],						\
3988   &mips_reg_names[90][0],						\
3989   &mips_reg_names[91][0],						\
3990   &mips_reg_names[92][0],						\
3991   &mips_reg_names[93][0],						\
3992   &mips_reg_names[94][0],						\
3993   &mips_reg_names[95][0],						\
3994   &mips_reg_names[96][0],						\
3995   &mips_reg_names[97][0],						\
3996   &mips_reg_names[98][0],						\
3997   &mips_reg_names[99][0],						\
3998   &mips_reg_names[100][0],						\
3999   &mips_reg_names[101][0],						\
4000   &mips_reg_names[102][0],						\
4001   &mips_reg_names[103][0],						\
4002   &mips_reg_names[104][0],						\
4003   &mips_reg_names[105][0],						\
4004   &mips_reg_names[106][0],						\
4005   &mips_reg_names[107][0],						\
4006   &mips_reg_names[108][0],						\
4007   &mips_reg_names[109][0],						\
4008   &mips_reg_names[110][0],						\
4009   &mips_reg_names[111][0],						\
4010   &mips_reg_names[112][0],						\
4011   &mips_reg_names[113][0],						\
4012   &mips_reg_names[114][0],						\
4013   &mips_reg_names[115][0],						\
4014   &mips_reg_names[116][0],						\
4015   &mips_reg_names[117][0],						\
4016   &mips_reg_names[118][0],						\
4017   &mips_reg_names[119][0],						\
4018   &mips_reg_names[120][0],						\
4019   &mips_reg_names[121][0],						\
4020   &mips_reg_names[122][0],						\
4021   &mips_reg_names[123][0],						\
4022   &mips_reg_names[124][0],						\
4023   &mips_reg_names[125][0],						\
4024   &mips_reg_names[126][0],						\
4025   &mips_reg_names[127][0],						\
4026   &mips_reg_names[128][0],						\
4027   &mips_reg_names[129][0],						\
4028   &mips_reg_names[130][0],						\
4029   &mips_reg_names[131][0],						\
4030   &mips_reg_names[132][0],						\
4031   &mips_reg_names[133][0],						\
4032   &mips_reg_names[134][0],						\
4033   &mips_reg_names[135][0],						\
4034   &mips_reg_names[136][0],						\
4035   &mips_reg_names[137][0],						\
4036   &mips_reg_names[138][0],						\
4037   &mips_reg_names[139][0],						\
4038   &mips_reg_names[140][0],						\
4039   &mips_reg_names[141][0],						\
4040   &mips_reg_names[142][0],						\
4041   &mips_reg_names[143][0],						\
4042   &mips_reg_names[144][0],						\
4043   &mips_reg_names[145][0],						\
4044   &mips_reg_names[146][0],						\
4045   &mips_reg_names[147][0],						\
4046   &mips_reg_names[148][0],						\
4047   &mips_reg_names[149][0],						\
4048   &mips_reg_names[150][0],						\
4049   &mips_reg_names[151][0],						\
4050   &mips_reg_names[152][0],						\
4051   &mips_reg_names[153][0],						\
4052   &mips_reg_names[154][0],						\
4053   &mips_reg_names[155][0],						\
4054   &mips_reg_names[156][0],						\
4055   &mips_reg_names[157][0],						\
4056   &mips_reg_names[158][0],						\
4057   &mips_reg_names[159][0],						\
4058   &mips_reg_names[160][0],						\
4059   &mips_reg_names[161][0],						\
4060   &mips_reg_names[162][0],						\
4061   &mips_reg_names[163][0],						\
4062   &mips_reg_names[164][0],						\
4063   &mips_reg_names[165][0],						\
4064   &mips_reg_names[166][0],						\
4065   &mips_reg_names[167][0],						\
4066   &mips_reg_names[168][0],						\
4067   &mips_reg_names[169][0],						\
4068   &mips_reg_names[170][0],						\
4069   &mips_reg_names[171][0],						\
4070   &mips_reg_names[172][0],						\
4071   &mips_reg_names[173][0],						\
4072   &mips_reg_names[174][0],						\
4073   &mips_reg_names[175][0]						\
4074 }
4075 
4076 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
4077    So define this for it.  */
4078 #define DEBUG_REGISTER_NAMES						\
4079 {									\
4080   "$0",   "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",		\
4081   "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",		\
4082   "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",		\
4083   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "$fp",  "ra",		\
4084   "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",	\
4085   "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",	\
4086   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",	\
4087   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",	\
4088   "hi",   "lo",   "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",	\
4089   "$fcc5","$fcc6","$fcc7","$rap", "",     "",     "",     "",		\
4090   "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
4091   "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
4092   "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
4093   "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
4094   "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
4095   "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
4096   "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
4097   "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
4098   "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
4099   "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
4100   "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
4101   "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
4102 }
4103 
4104 /* If defined, a C initializer for an array of structures
4105    containing a name and a register number.  This macro defines
4106    additional names for hard registers, thus allowing the `asm'
4107    option in declarations to refer to registers using alternate
4108    names.
4109 
4110    We define both names for the integer registers here.  */
4111 
4112 #define ADDITIONAL_REGISTER_NAMES					\
4113 {									\
4114   { "$0",	 0 + GP_REG_FIRST },					\
4115   { "$1",	 1 + GP_REG_FIRST },					\
4116   { "$2",	 2 + GP_REG_FIRST },					\
4117   { "$3",	 3 + GP_REG_FIRST },					\
4118   { "$4",	 4 + GP_REG_FIRST },					\
4119   { "$5",	 5 + GP_REG_FIRST },					\
4120   { "$6",	 6 + GP_REG_FIRST },					\
4121   { "$7",	 7 + GP_REG_FIRST },					\
4122   { "$8",	 8 + GP_REG_FIRST },					\
4123   { "$9",	 9 + GP_REG_FIRST },					\
4124   { "$10",	10 + GP_REG_FIRST },					\
4125   { "$11",	11 + GP_REG_FIRST },					\
4126   { "$12",	12 + GP_REG_FIRST },					\
4127   { "$13",	13 + GP_REG_FIRST },					\
4128   { "$14",	14 + GP_REG_FIRST },					\
4129   { "$15",	15 + GP_REG_FIRST },					\
4130   { "$16",	16 + GP_REG_FIRST },					\
4131   { "$17",	17 + GP_REG_FIRST },					\
4132   { "$18",	18 + GP_REG_FIRST },					\
4133   { "$19",	19 + GP_REG_FIRST },					\
4134   { "$20",	20 + GP_REG_FIRST },					\
4135   { "$21",	21 + GP_REG_FIRST },					\
4136   { "$22",	22 + GP_REG_FIRST },					\
4137   { "$23",	23 + GP_REG_FIRST },					\
4138   { "$24",	24 + GP_REG_FIRST },					\
4139   { "$25",	25 + GP_REG_FIRST },					\
4140   { "$26",	26 + GP_REG_FIRST },					\
4141   { "$27",	27 + GP_REG_FIRST },					\
4142   { "$28",	28 + GP_REG_FIRST },					\
4143   { "$29",	29 + GP_REG_FIRST },					\
4144   { "$30",	30 + GP_REG_FIRST },					\
4145   { "$31",	31 + GP_REG_FIRST },					\
4146   { "$sp",	29 + GP_REG_FIRST },					\
4147   { "$fp",	30 + GP_REG_FIRST },					\
4148   { "at",	 1 + GP_REG_FIRST },					\
4149   { "v0",	 2 + GP_REG_FIRST },					\
4150   { "v1",	 3 + GP_REG_FIRST },					\
4151   { "a0",	 4 + GP_REG_FIRST },					\
4152   { "a1",	 5 + GP_REG_FIRST },					\
4153   { "a2",	 6 + GP_REG_FIRST },					\
4154   { "a3",	 7 + GP_REG_FIRST },					\
4155   { "t0",	 8 + GP_REG_FIRST },					\
4156   { "t1",	 9 + GP_REG_FIRST },					\
4157   { "t2",	10 + GP_REG_FIRST },					\
4158   { "t3",	11 + GP_REG_FIRST },					\
4159   { "t4",	12 + GP_REG_FIRST },					\
4160   { "t5",	13 + GP_REG_FIRST },					\
4161   { "t6",	14 + GP_REG_FIRST },					\
4162   { "t7",	15 + GP_REG_FIRST },					\
4163   { "s0",	16 + GP_REG_FIRST },					\
4164   { "s1",	17 + GP_REG_FIRST },					\
4165   { "s2",	18 + GP_REG_FIRST },					\
4166   { "s3",	19 + GP_REG_FIRST },					\
4167   { "s4",	20 + GP_REG_FIRST },					\
4168   { "s5",	21 + GP_REG_FIRST },					\
4169   { "s6",	22 + GP_REG_FIRST },					\
4170   { "s7",	23 + GP_REG_FIRST },					\
4171   { "t8",	24 + GP_REG_FIRST },					\
4172   { "t9",	25 + GP_REG_FIRST },					\
4173   { "k0",	26 + GP_REG_FIRST },					\
4174   { "k1",	27 + GP_REG_FIRST },					\
4175   { "gp",	28 + GP_REG_FIRST },					\
4176   { "sp",	29 + GP_REG_FIRST },					\
4177   { "fp",	30 + GP_REG_FIRST },					\
4178   { "ra",	31 + GP_REG_FIRST },					\
4179   { "$sp",	29 + GP_REG_FIRST },					\
4180   { "$fp",	30 + GP_REG_FIRST }					\
4181   ALL_COP_ADDITIONAL_REGISTER_NAMES					\
4182 }
4183 
4184 /* This is meant to be redefined in the host dependent files.  It is a
4185    set of alternative names and regnums for mips coprocessors.  */
4186 
4187 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
4188 
4189 /* A C compound statement to output to stdio stream STREAM the
4190    assembler syntax for an instruction operand X.  X is an RTL
4191    expression.
4192 
4193    CODE is a value that can be used to specify one of several ways
4194    of printing the operand.  It is used when identical operands
4195    must be printed differently depending on the context.  CODE
4196    comes from the `%' specification that was used to request
4197    printing of the operand.  If the specification was just `%DIGIT'
4198    then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4199    is the ASCII code for LTR.
4200 
4201    If X is a register, this macro should print the register's name.
4202    The names can be found in an array `reg_names' whose type is
4203    `char *[]'.  `reg_names' is initialized from `REGISTER_NAMES'.
4204 
4205    When the machine description has a specification `%PUNCT' (a `%'
4206    followed by a punctuation character), this macro is called with
4207    a null pointer for X and the punctuation character for CODE.
4208 
4209    See mips.c for the MIPS specific codes.  */
4210 
4211 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4212 
4213 /* A C expression which evaluates to true if CODE is a valid
4214    punctuation character for use in the `PRINT_OPERAND' macro.  If
4215    `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4216    punctuation characters (except for the standard one, `%') are
4217    used in this way.  */
4218 
4219 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4220 
4221 /* A C compound statement to output to stdio stream STREAM the
4222    assembler syntax for an instruction operand that is a memory
4223    reference whose address is ADDR.  ADDR is an RTL expression.  */
4224 
4225 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4226 
4227 
4228 /* A C statement, to be executed after all slot-filler instructions
4229    have been output.  If necessary, call `dbr_sequence_length' to
4230    determine the number of slots filled in a sequence (zero if not
4231    currently outputting a sequence), to decide how many no-ops to
4232    output, or whatever.
4233 
4234    Don't define this macro if it has nothing to do, but it is
4235    helpful in reading assembly output if the extent of the delay
4236    sequence is made explicit (e.g. with white space).
4237 
4238    Note that output routines for instructions with delay slots must
4239    be prepared to deal with not being output as part of a sequence
4240    (i.e.  when the scheduling pass is not run, or when no slot
4241    fillers could be found.)  The variable `final_sequence' is null
4242    when not processing a sequence, otherwise it contains the
4243    `sequence' rtx being output.  */
4244 
4245 #define DBR_OUTPUT_SEQEND(STREAM)					\
4246 do									\
4247   {									\
4248     if (set_nomacro > 0 && --set_nomacro == 0)				\
4249       fputs ("\t.set\tmacro\n", STREAM);				\
4250 									\
4251     if (set_noreorder > 0 && --set_noreorder == 0)			\
4252       fputs ("\t.set\treorder\n", STREAM);				\
4253 									\
4254     dslots_jump_filled++;						\
4255     fputs ("\n", STREAM);						\
4256   }									\
4257 while (0)
4258 
4259 
4260 /* How to tell the debugger about changes of source files.  Note, the
4261    mips ECOFF format cannot deal with changes of files inside of
4262    functions, which means the output of parser generators like bison
4263    is generally not debuggable without using the -l switch.  Lose,
4264    lose, lose.  Silicon graphics seems to want all .file's hardwired
4265    to 1.  */
4266 
4267 #ifndef SET_FILE_NUMBER
4268 #define SET_FILE_NUMBER() ++num_source_filenames
4269 #endif
4270 
4271 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME)			\
4272   mips_output_filename (STREAM, NAME)
4273 
4274 /* This is defined so that it can be overridden in iris6.h.  */
4275 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4276 do								\
4277   {								\
4278     fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES);	\
4279     output_quoted_string (STREAM, NAME);			\
4280     fputs ("\n", STREAM);					\
4281   }								\
4282 while (0)
4283 
4284 /* This is how to output a note the debugger telling it the line number
4285    to which the following sequence of instructions corresponds.
4286    Silicon graphics puts a label after each .loc.  */
4287 
4288 #ifndef LABEL_AFTER_LOC
4289 #define LABEL_AFTER_LOC(STREAM)
4290 #endif
4291 
4292 #ifndef ASM_OUTPUT_SOURCE_LINE
4293 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE)				\
4294   mips_output_lineno (STREAM, LINE)
4295 #endif
4296 
4297 /* The MIPS implementation uses some labels for its own purpose.  The
4298    following lists what labels are created, and are all formed by the
4299    pattern $L[a-z].*.  The machine independent portion of GCC creates
4300    labels matching:  $L[A-Z][0-9]+ and $L[0-9]+.
4301 
4302 	LM[0-9]+	Silicon Graphics/ECOFF stabs label before each stmt.
4303 	$Lb[0-9]+	Begin blocks for MIPS debug support
4304 	$Lc[0-9]+	Label for use in s<xx> operation.
4305 	$Le[0-9]+	End blocks for MIPS debug support  */
4306 
4307 /* A C statement (sans semicolon) to output to the stdio stream
4308    STREAM any text necessary for declaring the name NAME of an
4309    initialized variable which is being defined.  This macro must
4310    output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4311    The argument DECL is the `VAR_DECL' tree node representing the
4312    variable.
4313 
4314    If this macro is not defined, then the variable name is defined
4315    in the usual manner as a label (by means of `ASM_OUTPUT_LABEL').  */
4316 
4317 #undef ASM_DECLARE_OBJECT_NAME
4318 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL)			\
4319 do									\
4320  {									\
4321    mips_declare_object (STREAM, NAME, "", ":\n", 0);			\
4322  }									\
4323 while (0)
4324 
4325 /* Globalizing directive for a label.  */
4326 #define GLOBAL_ASM_OP "\t.globl\t"
4327 
4328 /* This says how to define a global common symbol.  */
4329 
4330 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
4331 
4332 /* This says how to define a local common symbol (ie, not visible to
4333    linker).  */
4334 
4335 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED)			\
4336   mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4337 
4338 
4339 /* This says how to output an external.  It would be possible not to
4340    output anything and let undefined symbol become external. However
4341    the assembler uses length information on externals to allocate in
4342    data/sdata bss/sbss, thereby saving exec time.  */
4343 
4344 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4345   mips_output_external(STREAM,DECL,NAME)
4346 
4347 /* This says what to print at the end of the assembly file */
4348 #undef ASM_FILE_END
4349 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4350 
4351 
4352 /* Play switch file games if we're optimizing the global pointer.  */
4353 
4354 #undef TEXT_SECTION
4355 #define TEXT_SECTION()					\
4356 do {							\
4357   extern FILE *asm_out_text_file;			\
4358   if (TARGET_FILE_SWITCHING)				\
4359     asm_out_file = asm_out_text_file;			\
4360   fputs (TEXT_SECTION_ASM_OP, asm_out_file);		\
4361   fputc ('\n', asm_out_file);            		\
4362 } while (0)
4363 
4364 
4365 /* This is how to declare a function name.  The actual work of
4366    emitting the label is moved to function_prologue, so that we can
4367    get the line number correctly emitted before the .ent directive,
4368    and after any .file directives.  Define as empty so that the function
4369    is not declared before the .ent directive elsewhere.  */
4370 
4371 #undef ASM_DECLARE_FUNCTION_NAME
4372 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
4373 
4374 
4375 /* This is how to output an internal numbered label where
4376    PREFIX is the class of label and NUM is the number within the class.  */
4377 
4378 #undef ASM_OUTPUT_INTERNAL_LABEL
4379 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM)			\
4380   fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4381 
4382 /* This is how to store into the string LABEL
4383    the symbol_ref name of an internal numbered label where
4384    PREFIX is the class of label and NUM is the number within the class.
4385    This is suitable for output with `assemble_name'.  */
4386 
4387 #undef ASM_GENERATE_INTERNAL_LABEL
4388 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)			\
4389   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4390 
4391 /* This is how to output an element of a case-vector that is absolute.  */
4392 
4393 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)				\
4394   fprintf (STREAM, "\t%s\t%sL%d\n",					\
4395 	   Pmode == DImode ? ".dword" : ".word",			\
4396 	   LOCAL_LABEL_PREFIX,						\
4397 	   VALUE)
4398 
4399 /* This is how to output an element of a case-vector that is relative.
4400    This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4401    TARGET_EMBEDDED_PIC).  */
4402 
4403 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)		\
4404 do {									\
4405   if (TARGET_MIPS16)							\
4406     fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n",				\
4407 	     LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL);	\
4408   else if (TARGET_EMBEDDED_PIC)						\
4409     fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n",				\
4410 	     Pmode == DImode ? ".dword" : ".word",			\
4411 	     LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL);	\
4412   else if (mips_abi == ABI_32 || mips_abi == ABI_O64)			\
4413     fprintf (STREAM, "\t%s\t%sL%d\n",					\
4414 	     Pmode == DImode ? ".gpdword" : ".gpword",			\
4415 	     LOCAL_LABEL_PREFIX, VALUE);				\
4416   else									\
4417     fprintf (STREAM, "\t%s\t%sL%d\n",					\
4418 	     Pmode == DImode ? ".dword" : ".word",			\
4419 	     LOCAL_LABEL_PREFIX, VALUE);				\
4420 } while (0)
4421 
4422 /* When generating embedded PIC or mips16 code we want to put the jump
4423    table in the .text section.  In all other cases, we want to put the
4424    jump table in the .rdata section.  Unfortunately, we can't use
4425    JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4426    Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4427    section if appropriate.  */
4428 #undef ASM_OUTPUT_CASE_LABEL
4429 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN)			\
4430 do {									\
4431   if (TARGET_EMBEDDED_PIC || TARGET_MIPS16)				\
4432     function_section (current_function_decl);				\
4433   ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM);			\
4434 } while (0)
4435 
4436 /* This is how to output an assembler line
4437    that says to advance the location counter
4438    to a multiple of 2**LOG bytes.  */
4439 
4440 #define ASM_OUTPUT_ALIGN(STREAM,LOG)					\
4441   fprintf (STREAM, "\t.align\t%d\n", (LOG))
4442 
4443 /* This is how to output an assembler line to advance the location
4444    counter by SIZE bytes.  */
4445 
4446 #undef ASM_OUTPUT_SKIP
4447 #define ASM_OUTPUT_SKIP(STREAM,SIZE)					\
4448   fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4449 
4450 /* This is how to output a string.  */
4451 #undef ASM_OUTPUT_ASCII
4452 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN)				\
4453   mips_output_ascii (STREAM, STRING, LEN)
4454 
4455 /* Output #ident as a in the read-only data section.  */
4456 #undef  ASM_OUTPUT_IDENT
4457 #define ASM_OUTPUT_IDENT(FILE, STRING)					\
4458 {									\
4459   const char *p = STRING;						\
4460   int size = strlen (p) + 1;						\
4461   readonly_data_section ();						\
4462   assemble_string (p, size);						\
4463 }
4464 
4465 /* Default to -G 8 */
4466 #ifndef MIPS_DEFAULT_GVALUE
4467 #define MIPS_DEFAULT_GVALUE 8
4468 #endif
4469 
4470 /* Define the strings to put out for each section in the object file.  */
4471 #define TEXT_SECTION_ASM_OP	"\t.text"	/* instructions */
4472 #define DATA_SECTION_ASM_OP	"\t.data"	/* large data */
4473 #define SDATA_SECTION_ASM_OP	"\t.sdata"	/* small data */
4474 
4475 #undef READONLY_DATA_SECTION_ASM_OP
4476 #define READONLY_DATA_SECTION_ASM_OP	"\t.rdata"	/* read-only data */
4477 
4478 #define SMALL_DATA_SECTION	sdata_section
4479 
4480 /* What other sections we support other than the normal .data/.text.  */
4481 
4482 #undef EXTRA_SECTIONS
4483 #define EXTRA_SECTIONS in_sdata
4484 
4485 /* Define the additional functions to select our additional sections.  */
4486 
4487 /* on the MIPS it is not a good idea to put constants in the text
4488    section, since this defeats the sdata/data mechanism. This is
4489    especially true when -O is used. In this case an effort is made to
4490    address with faster (gp) register relative addressing, which can
4491    only get at sdata and sbss items (there is no stext !!)  However,
4492    if the constant is too large for sdata, and it's readonly, it
4493    will go into the .rdata section.  */
4494 
4495 #undef EXTRA_SECTION_FUNCTIONS
4496 #define EXTRA_SECTION_FUNCTIONS						\
4497 void									\
4498 sdata_section ()							\
4499 {									\
4500   if (in_section != in_sdata)						\
4501     {									\
4502       fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP);		\
4503       in_section = in_sdata;						\
4504     }									\
4505 }
4506 
4507 /* Given a decl node or constant node, choose the section to output it in
4508    and select that section.  */
4509 
4510 #undef  TARGET_ASM_SELECT_SECTION
4511 #define TARGET_ASM_SELECT_SECTION  mips_select_section
4512 
4513 /* Store in OUTPUT a string (made with alloca) containing
4514    an assembler-name for a local static variable named NAME.
4515    LABELNO is an integer which is different for each call.  */
4516 
4517 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)			\
4518 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),			\
4519   sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4520 
4521 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO)				\
4522 do									\
4523   {									\
4524     fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n",			\
4525 	     TARGET_64BIT ? "dsubu" : "subu",				\
4526 	     reg_names[STACK_POINTER_REGNUM],				\
4527 	     reg_names[STACK_POINTER_REGNUM],				\
4528 	     TARGET_64BIT ? "sd" : "sw",				\
4529 	     reg_names[REGNO],						\
4530 	     reg_names[STACK_POINTER_REGNUM]);				\
4531   }									\
4532 while (0)
4533 
4534 #define ASM_OUTPUT_REG_POP(STREAM,REGNO)				\
4535 do									\
4536   {									\
4537     if (! set_noreorder)						\
4538       fprintf (STREAM, "\t.set\tnoreorder\n");				\
4539 									\
4540     dslots_load_total++;						\
4541     dslots_load_filled++;						\
4542     fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n",			\
4543 	     TARGET_64BIT ? "ld" : "lw",				\
4544 	     reg_names[REGNO],						\
4545 	     reg_names[STACK_POINTER_REGNUM],				\
4546 	     TARGET_64BIT ? "daddu" : "addu",				\
4547 	     reg_names[STACK_POINTER_REGNUM],				\
4548 	     reg_names[STACK_POINTER_REGNUM]);				\
4549 									\
4550     if (! set_noreorder)						\
4551       fprintf (STREAM, "\t.set\treorder\n");				\
4552   }									\
4553 while (0)
4554 
4555 /* How to start an assembler comment.
4556    The leading space is important (the mips native assembler requires it).  */
4557 #ifndef ASM_COMMENT_START
4558 #define ASM_COMMENT_START " #"
4559 #endif
4560 
4561 
4562 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4563    and mips-tdump.c to print them out.
4564 
4565    These must match the corresponding definitions in gdb/mipsread.c.
4566    Unfortunately, gcc and gdb do not currently share any directories.  */
4567 
4568 #define CODE_MASK 0x8F300
4569 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4570 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4571 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4572 
4573 
4574 /* Default definitions for size_t and ptrdiff_t.  We must override the
4575    definitions from ../svr4.h on mips-*-linux-gnu.  */
4576 
4577 #undef SIZE_TYPE
4578 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4579 
4580 #undef PTRDIFF_TYPE
4581 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4582 
4583 /* See mips_expand_prologue's use of loadgp for when this should be
4584    true.  */
4585 
4586 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS 		\
4587 					 && mips_abi != ABI_32		\
4588 					 && mips_abi != ABI_O64)
4589 
4590 /* In mips16 mode, we need to look through the function to check for
4591    PC relative loads that are out of range.  */
4592 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4593 
4594 /* We need to use a special set of functions to handle hard floating
4595    point code in mips16 mode.  */
4596 
4597 #ifndef INIT_SUBTARGET_OPTABS
4598 #define INIT_SUBTARGET_OPTABS
4599 #endif
4600 
4601 #define INIT_TARGET_OPTABS						\
4602 do									\
4603   {									\
4604     if (! TARGET_MIPS16 || ! mips16_hard_float)				\
4605       INIT_SUBTARGET_OPTABS;						\
4606     else								\
4607       {									\
4608 	add_optab->handlers[(int) SFmode].libfunc =			\
4609 	  init_one_libfunc ("__mips16_addsf3");				\
4610 	sub_optab->handlers[(int) SFmode].libfunc =			\
4611 	  init_one_libfunc ("__mips16_subsf3");				\
4612 	smul_optab->handlers[(int) SFmode].libfunc =			\
4613 	  init_one_libfunc ("__mips16_mulsf3");				\
4614 	sdiv_optab->handlers[(int) SFmode].libfunc =			\
4615 	  init_one_libfunc ("__mips16_divsf3");				\
4616 									\
4617 	eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2");		\
4618 	nesf2_libfunc = init_one_libfunc ("__mips16_nesf2");		\
4619 	gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2");		\
4620 	gesf2_libfunc = init_one_libfunc ("__mips16_gesf2");		\
4621 	ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2");		\
4622 	lesf2_libfunc = init_one_libfunc ("__mips16_lesf2");		\
4623 									\
4624 	floatsisf_libfunc =						\
4625 	  init_one_libfunc ("__mips16_floatsisf");			\
4626 	fixsfsi_libfunc =						\
4627 	  init_one_libfunc ("__mips16_fixsfsi");			\
4628 									\
4629 	if (TARGET_DOUBLE_FLOAT)					\
4630 	  {								\
4631 	    add_optab->handlers[(int) DFmode].libfunc =			\
4632 	      init_one_libfunc ("__mips16_adddf3");			\
4633 	    sub_optab->handlers[(int) DFmode].libfunc =			\
4634 	      init_one_libfunc ("__mips16_subdf3");			\
4635 	    smul_optab->handlers[(int) DFmode].libfunc =		\
4636 	      init_one_libfunc ("__mips16_muldf3");			\
4637 	    sdiv_optab->handlers[(int) DFmode].libfunc =		\
4638 	      init_one_libfunc ("__mips16_divdf3");			\
4639 									\
4640 	    extendsfdf2_libfunc =					\
4641 	      init_one_libfunc ("__mips16_extendsfdf2");		\
4642 	    truncdfsf2_libfunc =					\
4643 	      init_one_libfunc ("__mips16_truncdfsf2");			\
4644 									\
4645 	    eqdf2_libfunc =						\
4646 	      init_one_libfunc ("__mips16_eqdf2");			\
4647 	    nedf2_libfunc =						\
4648 	      init_one_libfunc ("__mips16_nedf2");			\
4649 	    gtdf2_libfunc =						\
4650 	      init_one_libfunc ("__mips16_gtdf2");			\
4651 	    gedf2_libfunc =						\
4652 	      init_one_libfunc ("__mips16_gedf2");			\
4653 	    ltdf2_libfunc =						\
4654 	      init_one_libfunc ("__mips16_ltdf2");			\
4655 	    ledf2_libfunc =						\
4656 	      init_one_libfunc ("__mips16_ledf2");			\
4657 									\
4658 	    floatsidf_libfunc =						\
4659 	      init_one_libfunc ("__mips16_floatsidf");			\
4660 	    fixdfsi_libfunc =						\
4661 	      init_one_libfunc ("__mips16_fixdfsi");			\
4662 	  }								\
4663       }									\
4664   }									\
4665 while (0)
4666 
4667 #define DFMODE_NAN \
4668 	unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
4669 	unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
4670 #define SFMODE_NAN \
4671 	unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
4672 	unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
4673 
4674 /* Generate calls to memcpy, etc., not bcopy, etc.  */
4675 #define TARGET_MEM_FUNCTIONS
4676 
4677 #ifndef __mips16
4678 /* Since the bits of the _init and _fini function is spread across
4679    many object files, each potentially with its own GP, we must assume
4680    we need to load our GP.  We don't preserve $gp or $ra, since each
4681    init/fini chunk is supposed to initialize $gp, and crti/crtn
4682    already take care of preserving $ra and, when appropriate, $gp.  */
4683 #if _MIPS_SIM == _MIPS_SIM_ABI32
4684 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC)	\
4685    asm (SECTION_OP "\n\
4686 	.set noreorder\n\
4687 	bal 1f\n\
4688 	nop\n\
4689 1:	.cpload $31\n\
4690 	.set reorder\n\
4691 	jal " USER_LABEL_PREFIX #FUNC "\n\
4692 	" TEXT_SECTION_ASM_OP);
4693 #endif /* Switch to #elif when we're no longer limited by K&R C.  */
4694 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
4695    || (defined _ABI64 && _MIPS_SIM == _ABI64)
4696 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC)	\
4697    asm (SECTION_OP "\n\
4698 	.set noreorder\n\
4699 	bal 1f\n\
4700 	nop\n\
4701 1:	.set reorder\n\
4702 	.cpsetup $31, $2, 1b\n\
4703 	jal " USER_LABEL_PREFIX #FUNC "\n\
4704 	" TEXT_SECTION_ASM_OP);
4705 #endif
4706 #endif
4707