| /llvm-project/llvm/unittests/Analysis/ |
| H A D | AliasAnalysisTest.cpp | 178 auto *Load1 = new LoadInst(IntType, Addr, "load", BB); in TEST_F() local
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1444 areLoadsFromSameBasePtr(SDNode * Load1,SDNode * Load2,int64_t & Offset1,int64_t & Offset2) areLoadsFromSameBasePtr() argument
1458 shouldScheduleLoadsNear(SDNode * Load1,SDNode * Load2,int64_t Offset1,int64_t Offset2,unsigned NumLoads) shouldScheduleLoadsNear() argument
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| /llvm-project/llvm/unittests/Frontend/ |
| H A D | OpenMPIRBuilderTest.cpp | 1903 LoadInst *Load1 = Builder.CreateLoad(Alloc1->getAllocatedType(), Alloc1); TEST_F() local
2110 LoadInst *Load1 = Builder.CreateLoad(Alloc1->getAllocatedType(), Alloc1); TEST_F() local
6147 auto *Load1 = UserCodeBlock->getFirstNonPHI(); TEST_F() local
6299 auto *Load1 = UserCodeBlock->getFirstNonPHI(); TEST_F() local
[all...] |
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 1948 areLoadsFromSameBasePtr(SDNode * Load1,SDNode * Load2,int64_t & Offset1,int64_t & Offset2) const areLoadsFromSameBasePtr() argument
2015 shouldScheduleLoadsNear(SDNode * Load1,SDNode * Load2,int64_t Offset1,int64_t Offset2,unsigned NumLoads) const shouldScheduleLoadsNear() argument
[all...] |
| H A D | ARMISelLowering.cpp | 13658 LoadSDNode *Load1 = dyn_cast<LoadSDNode>(N1); TryDistrubutionADDVecReduce() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 8651 areLoadsFromSameBasePtr(SDNode * Load1,SDNode * Load2,int64_t & Offset1,int64_t & Offset2) const areLoadsFromSameBasePtr() argument
8777 shouldScheduleLoadsNear(SDNode * Load1,SDNode * Load2,int64_t Offset1,int64_t Offset2,unsigned NumLoads) const shouldScheduleLoadsNear() argument
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| H A D | X86ISelLowering.cpp | 51105 SDValue Load1 = combineLoad() local
[all...] |
| /llvm-project/llvm/lib/Transforms/Instrumentation/ |
| H A D | DataFlowSanitizer.cpp | 2319 Value *Load1 = loadShadowOriginSansLoadTracking() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 233 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode()) in areLoadsFromSameBasePtr() argument
595 shouldScheduleLoadsNear(SDNode * Load0,SDNode * Load1,int64_t Offset0,int64_t Offset1,unsigned NumLoads) const shouldScheduleLoadsNear() argument
[all...] |
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 3252 SDValue Load1 = DAG.getLoad(LoadTy, dl, Chain, Base1, WideMMO); LowerUnalignedLoad() local
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| H A D | HexagonISelLoweringHVX.cpp | 2994 SDValue Load1 = DAG.getLoad(SingleTy, dl, Chain, Base1, MOp1); SplitHvxMemOp() local
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 12816 LoadSDNode *Load1 = cast<LoadSDNode>(Op1); tryToFoldExtendSelectLoad() local
[all...] |