Searched defs:LoReg (Results 1 – 11 of 11) sorted by relevance
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
H A D | AVRRegisterInfo.cpp | 271 void AVRRegisterInfo::splitReg(Register Reg, Register &LoReg, in splitReg()
|
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonCopyToCombine.cpp | 767 Register LoReg = LoOperand.getReg(); in emitCombineIR() local 866 Register LoReg = LoOperand.getReg(); in emitCombineRR() local
|
H A D | HexagonFrameLowering.cpp | 1127 Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo); in insertCFIInstructionsAt() local
|
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 828 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
|
H A D | MipsSEFrameLowering.cpp | 308 Register LoReg = I->getOperand(1).getReg(); in expandBuildPairF64() local
|
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUInstructionSelector.cpp | 1873 Register LoReg = MRI->createVirtualRegister(DstRC); in selectG_TRUNC() local 2147 Register LoReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() local 2202 Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FNEG() local 2239 Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FABS() local 2529 Register LoReg = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() local
|
H A D | SILoadStoreOptimizer.cpp | 166 Register LoReg; member
|
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 1833 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { in CMSEPushCalleeSaves() local 1853 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4; in CMSEPushCalleeSaves() local
|
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 4963 unsigned LoReg, ROpc, MOpc; in Select() local 5042 unsigned LoReg, HiReg; in Select() local 5181 unsigned LoReg, HiReg, ClrReg; in Select() local
|
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 6229 Register LoReg = MI.getOperand(0).getReg(); in emitReadCycleWidePseudo() local 6265 Register LoReg = MI.getOperand(0).getReg(); in emitSplitF64Pseudo() local 6300 Register LoReg = MI.getOperand(1).getReg(); in emitBuildPairF64Pseudo() local
|
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 11970 Register LoReg = MI.getOperand(0).getReg(); in EmitInstrWithCustomInserter() local
|