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Searched defs:LoReg (Results 1 – 11 of 11) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.cpp271 void AVRRegisterInfo::splitReg(Register Reg, Register &LoReg, in splitReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonCopyToCombine.cpp767 Register LoReg = LoOperand.getReg(); in emitCombineIR() local
866 Register LoReg = LoOperand.getReg(); in emitCombineRR() local
H A DHexagonFrameLowering.cpp1127 Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo); in insertCFIInstructionsAt() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp828 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
H A DMipsSEFrameLowering.cpp308 Register LoReg = I->getOperand(1).getReg(); in expandBuildPairF64() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp1873 Register LoReg = MRI->createVirtualRegister(DstRC); in selectG_TRUNC() local
2147 Register LoReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() local
2202 Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FNEG() local
2239 Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FABS() local
2529 Register LoReg = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() local
H A DSILoadStoreOptimizer.cpp166 Register LoReg; member
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp1833 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { in CMSEPushCalleeSaves() local
1853 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4; in CMSEPushCalleeSaves() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4963 unsigned LoReg, ROpc, MOpc; in Select() local
5042 unsigned LoReg, HiReg; in Select() local
5181 unsigned LoReg, HiReg, ClrReg; in Select() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp6229 Register LoReg = MI.getOperand(0).getReg(); in emitReadCycleWidePseudo() local
6265 Register LoReg = MI.getOperand(0).getReg(); in emitSplitF64Pseudo() local
6300 Register LoReg = MI.getOperand(1).getReg(); in emitBuildPairF64Pseudo() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp11970 Register LoReg = MI.getOperand(0).getReg(); in EmitInstrWithCustomInserter() local