1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that ARM uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 15 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 16 17 #include "MCTargetDesc/ARMBaseInfo.h" 18 #include "llvm/ADT/SmallVector.h" 19 #include "llvm/ADT/StringRef.h" 20 #include "llvm/CodeGen/CallingConvLower.h" 21 #include "llvm/CodeGen/ISDOpcodes.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/SelectionDAGNodes.h" 24 #include "llvm/CodeGen/TargetLowering.h" 25 #include "llvm/CodeGen/ValueTypes.h" 26 #include "llvm/CodeGenTypes/MachineValueType.h" 27 #include "llvm/IR/Attributes.h" 28 #include "llvm/IR/CallingConv.h" 29 #include "llvm/IR/Function.h" 30 #include "llvm/IR/InlineAsm.h" 31 #include "llvm/Support/CodeGen.h" 32 #include <optional> 33 #include <utility> 34 35 namespace llvm { 36 37 class ARMSubtarget; 38 class DataLayout; 39 class FastISel; 40 class FunctionLoweringInfo; 41 class GlobalValue; 42 class InstrItineraryData; 43 class Instruction; 44 class IRBuilderBase; 45 class MachineBasicBlock; 46 class MachineInstr; 47 class SelectionDAG; 48 class TargetLibraryInfo; 49 class TargetMachine; 50 class TargetRegisterInfo; 51 class VectorType; 52 53 namespace ARMISD { 54 55 // ARM Specific DAG Nodes 56 enum NodeType : unsigned { 57 // Start the numbering where the builtin ops and target ops leave off. 58 FIRST_NUMBER = ISD::BUILTIN_OP_END, 59 60 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 61 // TargetExternalSymbol, and TargetGlobalAddress. 62 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in 63 // PIC mode. 64 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 65 66 // Add pseudo op to model memcpy for struct byval. 67 COPY_STRUCT_BYVAL, 68 69 CALL, // Function call. 70 CALL_PRED, // Function call that's predicable. 71 CALL_NOLINK, // Function call with branch not branch-and-link. 72 tSECALL, // CMSE non-secure function call. 73 t2CALL_BTI, // Thumb function call followed by BTI instruction. 74 BRCOND, // Conditional branch. 75 BR_JT, // Jumptable branch. 76 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 77 RET_GLUE, // Return with a flag operand. 78 SERET_GLUE, // CMSE Entry function return with a flag operand. 79 INTRET_GLUE, // Interrupt return with an LR-offset and a flag operand. 80 81 PIC_ADD, // Add with a PC operand and a PIC label. 82 83 ASRL, // MVE long arithmetic shift right. 84 LSRL, // MVE long shift right. 85 LSLL, // MVE long shift left. 86 87 CMP, // ARM compare instructions. 88 CMN, // ARM CMN instructions. 89 CMPZ, // ARM compare that sets only Z flag. 90 CMPFP, // ARM VFP compare instruction, sets FPSCR. 91 CMPFPE, // ARM VFP signalling compare instruction, sets FPSCR. 92 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 93 CMPFPEw0, // ARM VFP signalling compare against zero instruction, sets 94 // FPSCR. 95 FMSTAT, // ARM fmstat instruction. 96 97 CMOV, // ARM conditional move instructions. 98 99 SSAT, // Signed saturation 100 USAT, // Unsigned saturation 101 102 BCC_i64, 103 104 LSLS, // Flag-setting shift left. 105 LSRS1, // Flag-setting logical shift right by one bit. 106 ASRS1, // Flag-setting arithmetic shift right by one bit. 107 RRX, // Shift right one bit with carry in. 108 109 ADDC, // Add with carry 110 ADDE, // Add using carry 111 SUBC, // Sub with carry 112 SUBE, // Sub using carry 113 114 VMOVRRD, // double to two gprs. 115 VMOVDRR, // Two gprs to double. 116 VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr 117 118 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 119 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 120 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch. 121 122 TC_RETURN, // Tail call return pseudo. 123 124 THREAD_POINTER, 125 126 DYN_ALLOC, // Dynamic allocation on the stack. 127 128 MEMBARRIER_MCR, // Memory barrier (MCR) 129 130 PRELOAD, // Preload 131 132 WIN__CHKSTK, // Windows' __chkstk call to do stack probing. 133 WIN__DBZCHK, // Windows' divide by zero check 134 135 WLS, // Low-overhead loops, While Loop Start branch. See t2WhileLoopStart 136 WLSSETUP, // Setup for the iteration count of a WLS. See t2WhileLoopSetup. 137 LOOP_DEC, // Really a part of LE, performs the sub 138 LE, // Low-overhead loops, Loop End 139 140 PREDICATE_CAST, // Predicate cast for MVE i1 types 141 VECTOR_REG_CAST, // Reinterpret the current contents of a vector register 142 143 MVESEXT, // Legalization aids for extending a vector into two/four vectors. 144 MVEZEXT, // or truncating two/four vectors into one. Eventually becomes 145 MVETRUNC, // stack store/load sequence, if not optimized to anything else. 146 147 VCMP, // Vector compare. 148 VCMPZ, // Vector compare to zero. 149 VTST, // Vector test bits. 150 151 // Vector shift by vector 152 VSHLs, // ...left/right by signed 153 VSHLu, // ...left/right by unsigned 154 155 // Vector shift by immediate: 156 VSHLIMM, // ...left 157 VSHRsIMM, // ...right (signed) 158 VSHRuIMM, // ...right (unsigned) 159 160 // Vector rounding shift by immediate: 161 VRSHRsIMM, // ...right (signed) 162 VRSHRuIMM, // ...right (unsigned) 163 VRSHRNIMM, // ...right narrow 164 165 // Vector saturating shift by immediate: 166 VQSHLsIMM, // ...left (signed) 167 VQSHLuIMM, // ...left (unsigned) 168 VQSHLsuIMM, // ...left (signed to unsigned) 169 VQSHRNsIMM, // ...right narrow (signed) 170 VQSHRNuIMM, // ...right narrow (unsigned) 171 VQSHRNsuIMM, // ...right narrow (signed to unsigned) 172 173 // Vector saturating rounding shift by immediate: 174 VQRSHRNsIMM, // ...right narrow (signed) 175 VQRSHRNuIMM, // ...right narrow (unsigned) 176 VQRSHRNsuIMM, // ...right narrow (signed to unsigned) 177 178 // Vector shift and insert: 179 VSLIIMM, // ...left 180 VSRIIMM, // ...right 181 182 // Vector get lane (VMOV scalar to ARM core register) 183 // (These are used for 8- and 16-bit element types only.) 184 VGETLANEu, // zero-extend vector extract element 185 VGETLANEs, // sign-extend vector extract element 186 187 // Vector move immediate and move negated immediate: 188 VMOVIMM, 189 VMVNIMM, 190 191 // Vector move f32 immediate: 192 VMOVFPIMM, 193 194 // Move H <-> R, clearing top 16 bits 195 VMOVrh, 196 VMOVhr, 197 198 // Vector duplicate: 199 VDUP, 200 VDUPLANE, 201 202 // Vector shuffles: 203 VEXT, // extract 204 VREV64, // reverse elements within 64-bit doublewords 205 VREV32, // reverse elements within 32-bit words 206 VREV16, // reverse elements within 16-bit halfwords 207 VZIP, // zip (interleave) 208 VUZP, // unzip (deinterleave) 209 VTRN, // transpose 210 VTBL1, // 1-register shuffle with mask 211 VTBL2, // 2-register shuffle with mask 212 VMOVN, // MVE vmovn 213 214 // MVE Saturating truncates 215 VQMOVNs, // Vector (V) Saturating (Q) Move and Narrow (N), signed (s) 216 VQMOVNu, // Vector (V) Saturating (Q) Move and Narrow (N), unsigned (u) 217 218 // MVE float <> half converts 219 VCVTN, // MVE vcvt f32 -> f16, truncating into either the bottom or top 220 // lanes 221 VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes 222 223 // MVE VIDUP instruction, taking a start value and increment. 224 VIDUP, 225 226 // Vector multiply long: 227 VMULLs, // ...signed 228 VMULLu, // ...unsigned 229 230 VQDMULH, // MVE vqdmulh instruction 231 232 // MVE reductions 233 VADDVs, // sign- or zero-extend the elements of a vector to i32, 234 VADDVu, // add them all together, and return an i32 of their sum 235 VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask 236 VADDVpu, 237 VADDLVs, // sign- or zero-extend elements to i64 and sum, returning 238 VADDLVu, // the low and high 32-bit halves of the sum 239 VADDLVAs, // Same as VADDLV[su] but also add an input accumulator 240 VADDLVAu, // provided as low and high halves 241 VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask 242 VADDLVpu, 243 VADDLVAps, // Same as VADDLVp[su] but with a v4i1 predicate mask 244 VADDLVApu, 245 VMLAVs, // sign- or zero-extend the elements of two vectors to i32, multiply 246 VMLAVu, // them and add the results together, returning an i32 of the sum 247 VMLAVps, // Same as VMLAV[su] with a v4i1 predicate mask 248 VMLAVpu, 249 VMLALVs, // Same as VMLAV but with i64, returning the low and 250 VMLALVu, // high 32-bit halves of the sum 251 VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask 252 VMLALVpu, 253 VMLALVAs, // Same as VMLALV but also add an input accumulator 254 VMLALVAu, // provided as low and high halves 255 VMLALVAps, // Same as VMLALVA[su] with a v4i1 predicate mask 256 VMLALVApu, 257 VMINVu, // Find minimum unsigned value of a vector and register 258 VMINVs, // Find minimum signed value of a vector and register 259 VMAXVu, // Find maximum unsigned value of a vector and register 260 VMAXVs, // Find maximum signed value of a vector and register 261 262 SMULWB, // Signed multiply word by half word, bottom 263 SMULWT, // Signed multiply word by half word, top 264 UMLAL, // 64bit Unsigned Accumulate Multiply 265 SMLAL, // 64bit Signed Accumulate Multiply 266 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply 267 SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16 268 SMLALBT, // 64-bit signed accumulate multiply bottom, top 16 269 SMLALTB, // 64-bit signed accumulate multiply top, bottom 16 270 SMLALTT, // 64-bit signed accumulate multiply top, top 16 271 SMLALD, // Signed multiply accumulate long dual 272 SMLALDX, // Signed multiply accumulate long dual exchange 273 SMLSLD, // Signed multiply subtract long dual 274 SMLSLDX, // Signed multiply subtract long dual exchange 275 SMMLAR, // Signed multiply long, round and add 276 SMMLSR, // Signed multiply long, subtract and round 277 278 // Single Lane QADD8 and QADD16. Only the bottom lane. That's what the b 279 // stands for. 280 QADD8b, 281 QSUB8b, 282 QADD16b, 283 QSUB16b, 284 UQADD8b, 285 UQSUB8b, 286 UQADD16b, 287 UQSUB16b, 288 289 // Operands of the standard BUILD_VECTOR node are not legalized, which 290 // is fine if BUILD_VECTORs are always lowered to shuffles or other 291 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 292 // operands need to be legalized. Define an ARM-specific version of 293 // BUILD_VECTOR for this purpose. 294 BUILD_VECTOR, 295 296 // Bit-field insert 297 BFI, 298 299 // Vector OR with immediate 300 VORRIMM, 301 // Vector AND with NOT of immediate 302 VBICIMM, 303 304 // Pseudo vector bitwise select 305 VBSP, 306 307 // Pseudo-instruction representing a memory copy using ldm/stm 308 // instructions. 309 MEMCPY, 310 311 // Pseudo-instruction representing a memory copy using a tail predicated 312 // loop 313 MEMCPYLOOP, 314 // Pseudo-instruction representing a memset using a tail predicated 315 // loop 316 MEMSETLOOP, 317 318 // V8.1MMainline condition select 319 CSINV, // Conditional select invert. 320 CSNEG, // Conditional select negate. 321 CSINC, // Conditional select increment. 322 323 // Vector load N-element structure to all lanes: 324 FIRST_MEMORY_OPCODE, 325 VLD1DUP = FIRST_MEMORY_OPCODE, 326 VLD2DUP, 327 VLD3DUP, 328 VLD4DUP, 329 330 // NEON loads with post-increment base updates: 331 VLD1_UPD, 332 VLD2_UPD, 333 VLD3_UPD, 334 VLD4_UPD, 335 VLD2LN_UPD, 336 VLD3LN_UPD, 337 VLD4LN_UPD, 338 VLD1DUP_UPD, 339 VLD2DUP_UPD, 340 VLD3DUP_UPD, 341 VLD4DUP_UPD, 342 VLD1x2_UPD, 343 VLD1x3_UPD, 344 VLD1x4_UPD, 345 346 // NEON stores with post-increment base updates: 347 VST1_UPD, 348 VST2_UPD, 349 VST3_UPD, 350 VST4_UPD, 351 VST2LN_UPD, 352 VST3LN_UPD, 353 VST4LN_UPD, 354 VST1x2_UPD, 355 VST1x3_UPD, 356 VST1x4_UPD, 357 358 // Load/Store of dual registers 359 LDRD, 360 STRD, 361 LAST_MEMORY_OPCODE = STRD, 362 }; 363 364 } // end namespace ARMISD 365 366 namespace ARM { 367 /// Possible values of current rounding mode, which is specified in bits 368 /// 23:22 of FPSCR. 369 enum Rounding { 370 RN = 0, // Round to Nearest 371 RP = 1, // Round towards Plus infinity 372 RM = 2, // Round towards Minus infinity 373 RZ = 3, // Round towards Zero 374 rmMask = 3 // Bit mask selecting rounding mode 375 }; 376 377 // Bit position of rounding mode bits in FPSCR. 378 const unsigned RoundingBitsPos = 22; 379 380 // Bits of floating-point status. These are NZCV flags, QC bit and cumulative 381 // FP exception bits. 382 const unsigned FPStatusBits = 0xf800009f; 383 384 // Some bits in the FPSCR are not yet defined. They must be preserved when 385 // modifying the contents. 386 const unsigned FPReservedBits = 0x00006060; 387 } // namespace ARM 388 389 /// Define some predicates that are used for node matching. 390 namespace ARM { 391 392 bool isBitFieldInvertedMask(unsigned v); 393 394 } // end namespace ARM 395 396 //===--------------------------------------------------------------------===// 397 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 398 399 class ARMTargetLowering : public TargetLowering { 400 // Copying needed for an outgoing byval argument. 401 enum ByValCopyKind { 402 // Argument is already in the correct location, no copy needed. 403 NoCopy, 404 // Argument value is currently in the local stack frame, needs copying to 405 // outgoing arguemnt area. 406 CopyOnce, 407 // Argument value is currently in the outgoing argument area, but not at 408 // the correct offset, so needs copying via a temporary in local stack 409 // space. 410 CopyViaTemp, 411 }; 412 413 public: 414 explicit ARMTargetLowering(const TargetMachine &TM, 415 const ARMSubtarget &STI); 416 417 unsigned getJumpTableEncoding() const override; 418 bool useSoftFloat() const override; 419 420 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 421 422 /// ReplaceNodeResults - Replace the results of node with an illegal result 423 /// type with new values built out of custom code. 424 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 425 SelectionDAG &DAG) const override; 426 427 const char *getTargetNodeName(unsigned Opcode) const override; 428 429 bool isSelectSupported(SelectSupportKind Kind) const override { 430 // ARM does not support scalar condition selects on vectors. 431 return (Kind != ScalarCondVectorVal); 432 } 433 434 bool isReadOnly(const GlobalValue *GV) const; 435 436 /// getSetCCResultType - Return the value type to use for ISD::SETCC. 437 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 438 EVT VT) const override; 439 440 MachineBasicBlock * 441 EmitInstrWithCustomInserter(MachineInstr &MI, 442 MachineBasicBlock *MBB) const override; 443 444 void AdjustInstrPostInstrSelection(MachineInstr &MI, 445 SDNode *Node) const override; 446 447 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; 448 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const; 449 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const; 450 SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const; 451 SDValue PerformMVEExtCombine(SDNode *N, DAGCombinerInfo &DCI) const; 452 SDValue PerformMVETruncCombine(SDNode *N, DAGCombinerInfo &DCI) const; 453 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 454 455 bool SimplifyDemandedBitsForTargetNode(SDValue Op, 456 const APInt &OriginalDemandedBits, 457 const APInt &OriginalDemandedElts, 458 KnownBits &Known, 459 TargetLoweringOpt &TLO, 460 unsigned Depth) const override; 461 462 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override; 463 464 /// allowsMisalignedMemoryAccesses - Returns true if the target allows 465 /// unaligned memory accesses of the specified type. Returns whether it 466 /// is "fast" by reference in the second argument. 467 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, 468 Align Alignment, 469 MachineMemOperand::Flags Flags, 470 unsigned *Fast) const override; 471 472 EVT getOptimalMemOpType(const MemOp &Op, 473 const AttributeList &FuncAttributes) const override; 474 475 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; 476 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 477 bool isZExtFree(SDValue Val, EVT VT2) const override; 478 Type* shouldConvertSplatType(ShuffleVectorInst* SVI) const override; 479 480 bool isFNegFree(EVT VT) const override; 481 482 bool isVectorLoadExtDesirable(SDValue ExtVal) const override; 483 484 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override; 485 486 487 /// isLegalAddressingMode - Return true if the addressing mode represented 488 /// by AM is legal for this target, for a load/store of the specified type. 489 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 490 Type *Ty, unsigned AS, 491 Instruction *I = nullptr) const override; 492 493 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 494 495 /// Returns true if the addressing mode representing by AM is legal 496 /// for the Thumb1 target, for a load/store of the specified type. 497 bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 498 499 /// isLegalICmpImmediate - Return true if the specified immediate is legal 500 /// icmp immediate, that is the target has icmp instructions which can 501 /// compare a register against the immediate without having to materialize 502 /// the immediate into a register. 503 bool isLegalICmpImmediate(int64_t Imm) const override; 504 505 /// isLegalAddImmediate - Return true if the specified immediate is legal 506 /// add immediate, that is the target has add instructions which can 507 /// add a register and the immediate without having to materialize 508 /// the immediate into a register. 509 bool isLegalAddImmediate(int64_t Imm) const override; 510 511 /// getPreIndexedAddressParts - returns true by value, base pointer and 512 /// offset pointer and addressing mode by reference if the node's address 513 /// can be legally represented as pre-indexed load / store address. 514 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, 515 ISD::MemIndexedMode &AM, 516 SelectionDAG &DAG) const override; 517 518 /// getPostIndexedAddressParts - returns true by value, base pointer and 519 /// offset pointer and addressing mode by reference if this node can be 520 /// combined with a load / store to form a post-indexed load / store. 521 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 522 SDValue &Offset, ISD::MemIndexedMode &AM, 523 SelectionDAG &DAG) const override; 524 525 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, 526 const APInt &DemandedElts, 527 const SelectionDAG &DAG, 528 unsigned Depth) const override; 529 530 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, 531 const APInt &DemandedElts, 532 TargetLoweringOpt &TLO) const override; 533 534 bool ExpandInlineAsm(CallInst *CI) const override; 535 536 ConstraintType getConstraintType(StringRef Constraint) const override; 537 538 /// Examine constraint string and operand type and determine a weight value. 539 /// The operand object must already have been set up with the operand type. 540 ConstraintWeight getSingleConstraintMatchWeight( 541 AsmOperandInfo &info, const char *constraint) const override; 542 543 std::pair<unsigned, const TargetRegisterClass *> 544 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 545 StringRef Constraint, MVT VT) const override; 546 547 const char *LowerXConstraint(EVT ConstraintVT) const override; 548 549 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 550 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 551 /// true it means one of the asm constraint of the inline asm instruction 552 /// being processed is 'm'. 553 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, 554 std::vector<SDValue> &Ops, 555 SelectionDAG &DAG) const override; 556 557 InlineAsm::ConstraintCode 558 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 559 if (ConstraintCode == "Q") 560 return InlineAsm::ConstraintCode::Q; 561 if (ConstraintCode.size() == 2) { 562 if (ConstraintCode[0] == 'U') { 563 switch(ConstraintCode[1]) { 564 default: 565 break; 566 case 'm': 567 return InlineAsm::ConstraintCode::Um; 568 case 'n': 569 return InlineAsm::ConstraintCode::Un; 570 case 'q': 571 return InlineAsm::ConstraintCode::Uq; 572 case 's': 573 return InlineAsm::ConstraintCode::Us; 574 case 't': 575 return InlineAsm::ConstraintCode::Ut; 576 case 'v': 577 return InlineAsm::ConstraintCode::Uv; 578 case 'y': 579 return InlineAsm::ConstraintCode::Uy; 580 } 581 } 582 } 583 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 584 } 585 586 const ARMSubtarget* getSubtarget() const { 587 return Subtarget; 588 } 589 590 /// getRegClassFor - Return the register class that should be used for the 591 /// specified value type. 592 const TargetRegisterClass * 593 getRegClassFor(MVT VT, bool isDivergent = false) const override; 594 595 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, 596 Align &PrefAlign) const override; 597 598 /// createFastISel - This method returns a target specific FastISel object, 599 /// or null if the target does not support "fast" ISel. 600 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 601 const TargetLibraryInfo *libInfo) const override; 602 603 Sched::Preference getSchedulingPreference(SDNode *N) const override; 604 605 bool preferZeroCompareBranch() const override { return true; } 606 607 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override; 608 609 bool 610 isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 611 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 612 613 /// isFPImmLegal - Returns true if the target can instruction select the 614 /// specified FP immediate natively. If false, the legalizer will 615 /// materialize the FP immediate as a load from a constant pool. 616 bool isFPImmLegal(const APFloat &Imm, EVT VT, 617 bool ForCodeSize = false) const override; 618 619 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 620 const CallInst &I, 621 MachineFunction &MF, 622 unsigned Intrinsic) const override; 623 624 /// Returns true if it is beneficial to convert a load of a constant 625 /// to just the constant itself. 626 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 627 Type *Ty) const override; 628 629 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type 630 /// with this index. 631 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 632 unsigned Index) const override; 633 634 bool shouldFormOverflowOp(unsigned Opcode, EVT VT, 635 bool MathUsed) const override { 636 // Using overflow ops for overflow checks only should beneficial on ARM. 637 return TargetLowering::shouldFormOverflowOp(Opcode, VT, true); 638 } 639 640 bool shouldReassociateReduction(unsigned Opc, EVT VT) const override { 641 return Opc != ISD::VECREDUCE_ADD; 642 } 643 644 /// Returns true if an argument of type Ty needs to be passed in a 645 /// contiguous block of registers in calling convention CallConv. 646 bool functionArgumentNeedsConsecutiveRegisters( 647 Type *Ty, CallingConv::ID CallConv, bool isVarArg, 648 const DataLayout &DL) const override; 649 650 /// If a physical register, this returns the register that receives the 651 /// exception address on entry to an EH pad. 652 Register 653 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 654 655 /// If a physical register, this returns the register that receives the 656 /// exception typeid on entry to a landing pad. 657 Register 658 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 659 660 Instruction *makeDMB(IRBuilderBase &Builder, ARM_MB::MemBOpt Domain) const; 661 Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, 662 AtomicOrdering Ord) const override; 663 Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, 664 AtomicOrdering Ord) const override; 665 666 void 667 emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override; 668 669 Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, 670 AtomicOrdering Ord) const override; 671 Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, 672 AtomicOrdering Ord) const override; 673 674 unsigned getMaxSupportedInterleaveFactor() const override; 675 676 bool lowerInterleavedLoad(LoadInst *LI, 677 ArrayRef<ShuffleVectorInst *> Shuffles, 678 ArrayRef<unsigned> Indices, 679 unsigned Factor) const override; 680 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, 681 unsigned Factor) const override; 682 683 bool shouldInsertFencesForAtomic(const Instruction *I) const override; 684 TargetLoweringBase::AtomicExpansionKind 685 shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 686 TargetLoweringBase::AtomicExpansionKind 687 shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 688 TargetLoweringBase::AtomicExpansionKind 689 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 690 TargetLoweringBase::AtomicExpansionKind 691 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 692 693 bool useLoadStackGuardNode(const Module &M) const override; 694 695 void insertSSPDeclarations(Module &M) const override; 696 Value *getSDagStackGuard(const Module &M) const override; 697 Function *getSSPStackGuardCheck(const Module &M) const override; 698 699 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, 700 unsigned &Cost) const override; 701 702 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, 703 const MachineFunction &MF) const override { 704 // Do not merge to larger than i32. 705 return (MemVT.getSizeInBits() <= 32); 706 } 707 708 bool isCheapToSpeculateCttz(Type *Ty) const override; 709 bool isCheapToSpeculateCtlz(Type *Ty) const override; 710 711 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 712 return VT.isScalarInteger(); 713 } 714 715 bool supportSwiftError() const override { 716 return true; 717 } 718 719 bool hasStandaloneRem(EVT VT) const override { 720 return HasStandaloneRem; 721 } 722 723 ShiftLegalizationStrategy 724 preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, 725 unsigned ExpansionFactor) const override; 726 727 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const; 728 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const; 729 730 /// Returns true if \p VecTy is a legal interleaved access type. This 731 /// function checks the vector element type and the overall width of the 732 /// vector. 733 bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy, 734 Align Alignment, 735 const DataLayout &DL) const; 736 737 bool isMulAddWithConstProfitable(SDValue AddNode, 738 SDValue ConstNode) const override; 739 740 bool alignLoopsWithOptSize() const override; 741 742 /// Returns the number of interleaved accesses that will be generated when 743 /// lowering accesses of the given type. 744 unsigned getNumInterleavedAccesses(VectorType *VecTy, 745 const DataLayout &DL) const; 746 747 void finalizeLowering(MachineFunction &MF) const override; 748 749 /// Return the correct alignment for the current calling convention. 750 Align getABIAlignmentForCallingConv(Type *ArgTy, 751 const DataLayout &DL) const override; 752 753 bool isDesirableToCommuteWithShift(const SDNode *N, 754 CombineLevel Level) const override; 755 756 bool isDesirableToCommuteXorWithShift(const SDNode *N) const override; 757 758 bool shouldFoldConstantShiftPairToMask(const SDNode *N, 759 CombineLevel Level) const override; 760 761 bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, 762 EVT VT) const override; 763 764 bool preferIncOfAddToSubOfNot(EVT VT) const override; 765 766 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override; 767 768 bool isComplexDeinterleavingSupported() const override; 769 bool isComplexDeinterleavingOperationSupported( 770 ComplexDeinterleavingOperation Operation, Type *Ty) const override; 771 772 Value *createComplexDeinterleavingIR( 773 IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, 774 ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, 775 Value *Accumulator = nullptr) const override; 776 777 bool softPromoteHalfType() const override { return true; } 778 779 bool useFPRegsForHalfType() const override { return true; } 780 781 protected: 782 std::pair<const TargetRegisterClass *, uint8_t> 783 findRepresentativeClass(const TargetRegisterInfo *TRI, 784 MVT VT) const override; 785 786 private: 787 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 788 /// make the right decision when generating code for different targets. 789 const ARMSubtarget *Subtarget; 790 791 const TargetRegisterInfo *RegInfo; 792 793 const InstrItineraryData *Itins; 794 795 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper 796 // check. 797 bool InsertFencesForAtomic; 798 799 bool HasStandaloneRem = true; 800 801 void addTypeForNEON(MVT VT, MVT PromotedLdStVT); 802 void addDRTypeForNEON(MVT VT); 803 void addQRTypeForNEON(MVT VT); 804 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const; 805 806 using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>; 807 808 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, 809 SDValue &Arg, RegsToPassVector &RegsToPass, 810 CCValAssign &VA, CCValAssign &NextVA, 811 SDValue &StackPtr, 812 SmallVectorImpl<SDValue> &MemOpChains, 813 bool IsTailCall, 814 int SPDiff) const; 815 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 816 SDValue &Root, SelectionDAG &DAG, 817 const SDLoc &dl) const; 818 819 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC, 820 bool isVarArg) const; 821 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 822 bool isVarArg) const; 823 std::pair<SDValue, MachinePointerInfo> 824 computeAddrForCallArg(const SDLoc &dl, SelectionDAG &DAG, 825 const CCValAssign &VA, SDValue StackPtr, 826 bool IsTailCall, int SPDiff) const; 827 ByValCopyKind ByValNeedsCopyForTailCall(SelectionDAG &DAG, SDValue Src, 828 SDValue Dst, 829 ISD::ArgFlagsTy Flags) const; 830 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 831 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 832 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const; 833 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG, 834 const ARMSubtarget *Subtarget) const; 835 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 836 const ARMSubtarget *Subtarget) const; 837 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 838 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 839 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 840 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 841 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 842 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const; 843 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 844 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 845 SelectionDAG &DAG) const; 846 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 847 SelectionDAG &DAG, 848 TLSModel::Model model) const; 849 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 850 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const; 851 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 852 SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const; 853 SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const; 854 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 855 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 856 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 857 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 858 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 859 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 860 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 861 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 862 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 863 SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 864 SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 865 SDValue LowerSET_FPMODE(SDValue Op, SelectionDAG &DAG) const; 866 SDValue LowerRESET_FPMODE(SDValue Op, SelectionDAG &DAG) const; 867 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG, 868 const ARMSubtarget *ST) const; 869 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 870 const ARMSubtarget *ST) const; 871 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 872 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; 873 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const; 874 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const; 875 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed, 876 SmallVectorImpl<SDValue> &Results) const; 877 SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG, 878 const ARMSubtarget *Subtarget) const; 879 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed, 880 SDValue &Chain) const; 881 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const; 882 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 883 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 884 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 885 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 886 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 887 SDValue LowerFSETCC(SDValue Op, SelectionDAG &DAG) const; 888 SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const; 889 void LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results, 890 SelectionDAG &DAG) const; 891 SDValue LowerFP_TO_BF16(SDValue Op, SelectionDAG &DAG) const; 892 893 Register getRegisterByName(const char* RegName, LLT VT, 894 const MachineFunction &MF) const override; 895 896 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 897 SmallVectorImpl<SDNode *> &Created) const override; 898 899 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 900 EVT VT) const override; 901 902 SDValue MoveToHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, MVT ValVT, 903 SDValue Val) const; 904 SDValue MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, 905 MVT ValVT, SDValue Val) const; 906 907 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 908 909 SDValue LowerCallResult(SDValue Chain, SDValue InGlue, 910 CallingConv::ID CallConv, bool isVarArg, 911 const SmallVectorImpl<ISD::InputArg> &Ins, 912 const SDLoc &dl, SelectionDAG &DAG, 913 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 914 SDValue ThisVal, bool isCmseNSCall) const; 915 916 bool supportSplitCSR(MachineFunction *MF) const override { 917 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 918 MF->getFunction().hasFnAttribute(Attribute::NoUnwind); 919 } 920 921 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 922 void insertCopiesSplitCSR( 923 MachineBasicBlock *Entry, 924 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 925 926 bool splitValueIntoRegisterParts( 927 SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, 928 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) 929 const override; 930 931 SDValue joinRegisterPartsIntoValue( 932 SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts, 933 unsigned NumParts, MVT PartVT, EVT ValueVT, 934 std::optional<CallingConv::ID> CC) const override; 935 936 SDValue 937 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 938 const SmallVectorImpl<ISD::InputArg> &Ins, 939 const SDLoc &dl, SelectionDAG &DAG, 940 SmallVectorImpl<SDValue> &InVals) const override; 941 942 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl, 943 SDValue &Chain, const Value *OrigArg, 944 unsigned InRegsParamRecordIdx, int ArgOffset, 945 unsigned ArgSize) const; 946 947 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 948 const SDLoc &dl, SDValue &Chain, 949 unsigned ArgOffset, unsigned TotalArgRegsSaveSize, 950 bool ForceMutable = false) const; 951 952 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 953 SmallVectorImpl<SDValue> &InVals) const override; 954 955 /// HandleByVal - Target-specific cleanup for ByVal support. 956 void HandleByVal(CCState *, unsigned &, Align) const override; 957 958 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 959 /// for tail call optimization. Targets which want to do tail call 960 /// optimization should implement this function. 961 bool IsEligibleForTailCallOptimization( 962 TargetLowering::CallLoweringInfo &CLI, CCState &CCInfo, 963 SmallVectorImpl<CCValAssign> &ArgLocs, const bool isIndirect) const; 964 965 bool CanLowerReturn(CallingConv::ID CallConv, 966 MachineFunction &MF, bool isVarArg, 967 const SmallVectorImpl<ISD::OutputArg> &Outs, 968 LLVMContext &Context, const Type *RetTy) const override; 969 970 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 971 const SmallVectorImpl<ISD::OutputArg> &Outs, 972 const SmallVectorImpl<SDValue> &OutVals, 973 const SDLoc &dl, SelectionDAG &DAG) const override; 974 975 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; 976 977 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 978 979 bool shouldConsiderGEPOffsetSplit() const override { return true; } 980 981 bool isUnsupportedFloatingType(EVT VT) const; 982 983 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal, 984 SDValue ARMcc, SDValue Flags, SelectionDAG &DAG) const; 985 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 986 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const; 987 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 988 const SDLoc &dl, bool Signaling = false) const; 989 990 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 991 992 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, 993 MachineBasicBlock *DispatchBB, int FI) const; 994 995 void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const; 996 997 MachineBasicBlock *EmitStructByval(MachineInstr &MI, 998 MachineBasicBlock *MBB) const; 999 1000 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI, 1001 MachineBasicBlock *MBB) const; 1002 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI, 1003 MachineBasicBlock *MBB) const; 1004 void addMVEVectorTypes(bool HasMVEFP); 1005 void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action); 1006 void setAllExpand(MVT VT); 1007 }; 1008 1009 enum VMOVModImmType { 1010 VMOVModImm, 1011 VMVNModImm, 1012 MVEVMVNModImm, 1013 OtherModImm 1014 }; 1015 1016 namespace ARM { 1017 1018 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 1019 const TargetLibraryInfo *libInfo); 1020 1021 } // end namespace ARM 1022 1023 } // end namespace llvm 1024 1025 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 1026