Searched defs:LHS1 (Results 1 – 9 of 9) sorted by relevance
| /llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 1314 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); matchIsFiniteTest() local
1332 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); foldLogicOfFCmps() local
3242 Value *LHS1 = LHS->getOperand(1), *RHS1 = RHS->getOperand(1); foldAndOrOfICmps() local
4054 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); foldXorOfICmps() local
[all...] |
| /llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 829 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, getAVRCmp() local
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| /llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LICM.cpp | 2440 Value *LHS1, *LHS2, *RHS1, *RHS2; hoistMinMax() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1058 auto *LHS1 = dyn_cast<ConstantSDNode>(LHS.getOperand(1)); isDesirableToCommuteWithShift() local
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| /llvm-project/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 1866 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); simplifyAndOrOfFCmps() local
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 7118 Register LHS1 = Cmp1->getRHSReg(); tryFoldLogicOfFCmps() local
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 5710 SDValue LHS1, LHS2; OptimizeVFPBrcond() local
12248 Register LHS1 = MI.getOperand(1).getReg(); EmitInstrWithCustomInserter() local
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6184 SDValue LHS1 = LHS->getOperand(1); foldAndOrOfSETCC() local
[all...] |
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 23142 SDValue LHS1, LHS2; splitIntVSETCC() local
48488 SDValue LHS1 = LHS.getOperand(1); combineVectorHADDSUB() local
[all...] |