1 /* 2 * arm-specific definitions for cortex-a8 and -a9 3 * these are used in C and assembler 4 * 5 * `cortex' refers to the cortex-a8 or -a9. 6 */ 7 8 #define NREGS 15 /* general-purpose regs, R0 through R14 */ 9 10 /* 11 * Program Status Registers 12 */ 13 #define PsrMusr 0x00000010 /* mode */ 14 #define PsrMfiq 0x00000011 15 #define PsrMirq 0x00000012 16 #define PsrMsvc 0x00000013 /* `protected mode for OS' */ 17 #define PsrMmon 0x00000016 /* `secure monitor' (trustzone hyper) */ 18 #define PsrMabt 0x00000017 19 #define PsrMund 0x0000001B 20 #define PsrMsys 0x0000001F /* `privileged user mode for OS' (trustzone) */ 21 #define PsrMask 0x0000001F 22 23 #define PsrThumb 0x00000020 /* beware hammers */ 24 #define PsrDfiq 0x00000040 /* disable FIQ interrupts */ 25 #define PsrDirq 0x00000080 /* disable IRQ interrupts */ 26 #define PsrDasabt 0x00000100 /* disable asynch aborts */ 27 #define PsrBigend 0x00000200 28 29 #define PsrJaz 0x01000000 /* java mode */ 30 31 #define PsrV 0x10000000 /* overflow */ 32 #define PsrC 0x20000000 /* carry/borrow/extend */ 33 #define PsrZ 0x40000000 /* zero */ 34 #define PsrN 0x80000000 /* negative/less than */ 35 36 #define PsrMbz (PsrJaz|PsrThumb|PsrBigend) /* these bits must be 0 */ 37 38 /* 39 * MCR and MRC are anti-mnemonic. 40 * MTCP coproc, opcode1, Rd, CRn, CRm[, opcode2] # arm -> coproc 41 * MFCP coproc, opcode1, Rd, CRn, CRm[, opcode2] # coproc -> arm 42 */ 43 44 #define MTCP MCR 45 #define MFCP MRC 46 47 /* instruction decoding */ 48 #define ISCPOP(op) ((op) == 0xE || ((op) & ~1) == 0xC) 49 #define ISFPAOP(cp, op) ((cp) == CpOFPA && ISCPOP(op)) 50 #define ISVFPOP(cp, op) (((cp) == CpDFP || (cp) == CpFP) && ISCPOP(op)) 51 52 /* 53 * Coprocessors 54 */ 55 #define CpOFPA 1 /* ancient 7500 FPA */ 56 #define CpFP 10 /* float FP, VFP cfg. */ 57 #define CpDFP 11 /* double FP */ 58 #define CpSC 15 /* System Control */ 59 60 /* 61 * Primary (CRn) CpSC registers. 62 */ 63 #define CpID 0 /* ID and cache type */ 64 #define CpCONTROL 1 /* miscellaneous control */ 65 #define CpTTB 2 /* Translation Table Base(s) */ 66 #define CpDAC 3 /* Domain Access Control */ 67 #define CpFSR 5 /* Fault Status */ 68 #define CpFAR 6 /* Fault Address */ 69 #define CpCACHE 7 /* cache/write buffer control */ 70 #define CpTLB 8 /* TLB control */ 71 #define CpCLD 9 /* L2 Cache Lockdown, op1==1 */ 72 #define CpTLD 10 /* TLB Lockdown, with op2 */ 73 #define CpVECS 12 /* vector bases, op1==0, Crm==0, op2s (cortex) */ 74 #define CpPID 13 /* Process ID */ 75 #define CpDTLB 15 /* TLB, L1 cache stuff (cortex) */ 76 77 /* 78 * CpTTB op1==0, Crm==0 opcode2 values. 79 */ 80 #define CpTTB0 0 /* secure ttb */ 81 #define CpTTB1 1 /* non-secure ttb (v7) */ 82 #define CpTTBctl 2 /* v7 */ 83 84 /* 85 * CpFSR op1==0, Crm==0 opcode 2 values. 86 */ 87 #define CpDFSR 0 /* data fault status */ 88 #define CpIFSR 1 /* instruction fault status */ 89 90 /* 91 * CpFAR op1==0, Crm==0 opcode 2 values. 92 */ 93 #define CpDFAR 0 /* data fault address */ 94 #define CpIFAR 2 /* instruction fault address */ 95 96 /* 97 * CpID Secondary (CRm) registers. 98 */ 99 #define CpIDidct 0 100 101 /* 102 * CpID CpIDidct op1==0 opcode2 fields. 103 */ 104 #define CpIDid 0 /* main ID */ 105 #define CpIDct 1 /* cache type */ 106 #define CpIDtlb 3 /* tlb type (cortex) */ 107 #define CpIDmpid 5 /* multiprocessor id (cortex) */ 108 109 /* CpIDid op1 values */ 110 #define CpIDcsize 1 /* cache size (cortex) */ 111 #define CpIDcssel 2 /* cache size select (cortex) */ 112 113 /* 114 * CpID CpIDidct op1==CpIDcsize opcode2 fields. 115 */ 116 #define CpIDcasize 0 /* cache size */ 117 #define CpIDclvlid 1 /* cache-level id */ 118 119 /* 120 * CpCONTROL op2 codes, op1==0, Crm==0. 121 */ 122 #define CpMainctl 0 /* sctlr */ 123 #define CpAuxctl 1 124 #define CpCPaccess 2 125 126 /* 127 * CpCONTROL: op1==0, CRm==0, op2==CpMainctl. 128 * main control register. 129 * cortex/armv7 has more ops and CRm values. 130 */ 131 #define CpCmmu 0x00000001 /* M: MMU enable */ 132 #define CpCalign 0x00000002 /* A: alignment fault enable */ 133 #define CpCdcache 0x00000004 /* C: data cache on */ 134 #define CpBigend (1<<7) 135 #define CpCsw (1<<10) /* SW: SWP(B) enable (deprecated in v7) */ 136 #define CpCpredict 0x00000800 /* Z: branch prediction (armv7) */ 137 #define CpCicache 0x00001000 /* I: instruction cache on */ 138 #define CpChv 0x00002000 /* V: high vectors */ 139 #define CpCrr (1<<14) /* RR: round robin vs random cache replacement */ 140 #define CpCha (1<<17) /* HA: hw access flag enable */ 141 #define CpCdz (1<<19) /* DZ: divide by zero fault enable (not cortex-a9) */ 142 #define CpCfi (1<<21) /* FI: fast intrs */ 143 #define CpCve (1<<24) /* VE: intr vectors enable */ 144 #define CpCee (1<<25) /* EE: exception endianness: big */ 145 #define CpCnmfi (1<<27) /* NMFI: non-maskable fast intrs. (RO) */ 146 #define CpCtre (1<<28) /* TRE: TEX remap enable */ 147 #define CpCafe (1<<29) /* AFE: access flag (ttb) enable */ 148 #define CpCte (1<<30) /* TE: thumb exceptions */ 149 150 #define CpCsbz (1<<31 | CpCte | CpCafe | CpCtre | 1<<26 | CpCee | CpCve | \ 151 CpCfi | 3<<19 | CpCha | 1<<15 | 3<<8 | CpBigend) /* must be 0 (armv7) */ 152 #define CpCsbo (3<<22 | 1<<18 | 1<<16 | CpChv | CpCsw | 017<<3) /* must be 1 (armv7) */ 153 154 /* 155 * CpCONTROL: op1==0, CRm==0, op2==CpAuxctl. 156 * Auxiliary control register on cortex-a9. 157 * these differ from even the cortex-a8 bits. 158 */ 159 #define CpACparity (1<<9) 160 #define CpACca1way (1<<8) /* cache in a single way */ 161 #define CpACcaexcl (1<<7) /* exclusive cache */ 162 #define CpACsmp (1<<6) /* SMP l1 caches coherence; needed for ldrex/strex */ 163 #define CpAClwr0line (1<<3) /* write full cache line of 0s; see Fullline0 */ 164 #define CpACl1pref (1<<2) /* l1 prefetch enable */ 165 #define CpACl2pref (1<<1) /* l2 prefetch enable */ 166 #define CpACmaintbcast (1<<0) /* broadcast cache & tlb maint. ops */ 167 168 /* 169 * CpCONTROL Secondary (CRm) registers and opcode2 fields. 170 */ 171 #define CpCONTROLscr 1 172 173 #define CpSCRscr 0 /* secure configuration */ 174 175 /* 176 * CpCACHE Secondary (CRm) registers and opcode2 fields. op1==0. 177 * In ARM-speak, 'flush' means invalidate and 'clean' means writeback. 178 */ 179 #define CpCACHEintr 0 /* interrupt (op2==4) */ 180 #define CpCACHEisi 1 /* inner-sharable I cache (v7) */ 181 #define CpCACHEpaddr 4 /* 0: phys. addr (cortex) */ 182 #define CpCACHEinvi 5 /* instruction, branch table */ 183 #define CpCACHEinvd 6 /* data or unified */ 184 // #define CpCACHEinvu 7 /* unified (not on cortex) */ 185 #define CpCACHEva2pa 8 /* va -> pa translation (cortex) */ 186 #define CpCACHEwb 10 /* writeback */ 187 #define CpCACHEinvdse 11 /* data or unified by mva */ 188 #define CpCACHEwbi 14 /* writeback+invalidate */ 189 190 #define CpCACHEall 0 /* entire (not for invd nor wb(i) on cortex) */ 191 #define CpCACHEse 1 /* single entry */ 192 #define CpCACHEsi 2 /* set/index (set/way) */ 193 #define CpCACHEtest 3 /* test loop */ 194 #define CpCACHEwait 4 /* wait (prefetch flush on cortex) */ 195 #define CpCACHEdmbarr 5 /* wb only (cortex) */ 196 #define CpCACHEflushbtc 6 /* flush branch-target cache (cortex) */ 197 #define CpCACHEflushbtse 7 /* ⋯ or just one entry in it (cortex) */ 198 199 /* 200 * CpTLB Secondary (CRm) registers and opcode2 fields. 201 */ 202 #define CpTLBinvi 5 /* instruction */ 203 #define CpTLBinvd 6 /* data */ 204 #define CpTLBinvu 7 /* unified */ 205 206 #define CpTLBinv 0 /* invalidate all */ 207 #define CpTLBinvse 1 /* invalidate single entry */ 208 #define CpTBLasid 2 /* by ASID (cortex) */ 209 210 /* 211 * CpCLD Secondary (CRm) registers and opcode2 fields for op1==0. (cortex) 212 */ 213 #define CpCLDena 12 /* enables */ 214 #define CpCLDcyc 13 /* cycle counter */ 215 #define CpCLDuser 14 /* user enable */ 216 217 #define CpCLDenapmnc 0 218 #define CpCLDenacyc 1 219 220 /* 221 * CpCLD Secondary (CRm) registers and opcode2 fields for op1==1. 222 */ 223 #define CpCLDl2 0 /* l2 cache */ 224 225 #define CpCLDl2aux 2 /* auxiliary control */ 226 227 /* 228 * l2 cache aux. control 229 */ 230 #define CpCl2ecc (1<<28) /* use ecc, not parity */ 231 #define CpCl2noldforw (1<<27) /* no ld forwarding */ 232 #define CpCl2nowrcomb (1<<25) /* no write combining */ 233 #define CpCl2nowralldel (1<<24) /* no write allocate delay */ 234 #define CpCl2nowrallcomb (1<<23) /* no write allocate combine */ 235 #define CpCl2nowralloc (1<<22) /* no write allocate */ 236 #define CpCl2eccparity (1<<21) /* enable ecc or parity */ 237 #define CpCl2inner (1<<16) /* inner cacheability */ 238 /* other bits are tag ram & data ram latencies */ 239 240 /* 241 * CpTLD Secondary (CRm) registers and opcode2 fields. 242 */ 243 #define CpTLDlock 0 /* TLB lockdown registers */ 244 #define CpTLDpreload 1 /* TLB preload */ 245 246 #define CpTLDi 0 /* TLB instr. lockdown reg. */ 247 #define CpTLDd 1 /* " data " " */ 248 249 /* 250 * CpVECS Secondary (CRm) registers and opcode2 fields. 251 */ 252 #define CpVECSbase 0 253 254 #define CpVECSnorm 0 /* (non-)secure base addr */ 255 #define CpVECSmon 1 /* secure monitor base addr */ 256 257 /* 258 * MMU page table entries. 259 * memory must be cached, buffered, sharable and wralloc to participate in 260 * automatic L1 cache coherency. 261 */ 262 #define Mbz (0<<4) /* L1 page tables: must be 0 */ 263 #define Noexecsect (1<<4) /* L1 sections: no execute */ 264 #define Fault 0x00000000 /* L[12] pte: unmapped */ 265 266 #define Coarse (Mbz|1) /* L1: page table */ 267 #define Section (Mbz|2) /* L1 1MB */ 268 /* 269 * next 2 bits (L1wralloc & L1sharable) and Buffered and Cached must be 270 * set in l1 ptes for LDREX/STREX to work. 271 */ 272 #define L1wralloc (1<<12) /* L1 TEX */ 273 #define L1sharable (1<<16) 274 #define L1nonglobal (1<<17) /* tied to asid */ 275 #define Nonsecuresect (1<<19) /* L1 sections */ 276 277 #define Large 0x00000001 /* L2 64KB */ 278 #define Noexecsmall 1 /* L2: no execute */ 279 #define Small 0x00000002 /* L2 4KB */ 280 /* 281 * next 3 bits (Buffered, Cached, L2wralloc) & L2sharable must be set in 282 * l2 ptes for memory containing locks because LDREX/STREX require them. 283 */ 284 #define Buffered 0x00000004 /* L[12]: 0 write-thru, 1 -back */ 285 #define Cached 0x00000008 /* L[12] */ 286 #define L2wralloc (1<<6) /* L2 TEX (small pages) */ 287 #define L2apro (1<<9) /* L2 AP: read only */ 288 #define L2sharable (1<<10) 289 #define L2nonglobal (1<<11) /* tied to asid */ 290 #define Dom0 0 291 292 /* attributes for memory containing locks */ 293 #define L1ptedramattrs (Cached | Buffered | L1wralloc | L1sharable) 294 #define L2ptedramattrs (Cached | Buffered | L2wralloc | L2sharable) 295 296 #define Noaccess 0 /* AP, DAC */ 297 #define Krw 1 /* AP */ 298 /* armv7 deprecates AP[2] == 1 & AP[1:0] == 2 (Uro), prefers 3 (new in v7) */ 299 #define Uro 2 /* AP */ 300 #define Urw 3 /* AP */ 301 #define Client 1 /* DAC */ 302 #define Manager 3 /* DAC */ 303 304 #define AP(n, v) F((v), ((n)*2)+4, 2) 305 #define L1AP(ap) (AP(3, (ap))) 306 #define L2AP(ap) (AP(0, (ap))) /* armv7 */ 307 #define DAC(n, v) F((v), (n)*2, 2) 308 309 #define HVECTORS 0xffff0000 310