| /llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchExpandAtomicPseudoInsts.cpp | 302 expandAtomicBinOp(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,AtomicRMWInst::BinOp BinOp,bool IsMasked,int Width,MachineBasicBlock::iterator & NextMBBI) expandAtomicBinOp() argument
351 expandAtomicMinMaxOp(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,AtomicRMWInst::BinOp BinOp,bool IsMasked,int Width,MachineBasicBlock::iterator & NextMBBI) expandAtomicMinMaxOp() argument
470 expandAtomicCmpXchg(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,bool IsMasked,int Width,MachineBasicBlock::iterator & NextMBBI) expandAtomicCmpXchg() argument
[all...] |
| /llvm-project/clang/lib/Support/ |
| H A D | RISCVVIntrinsicUtils.cpp | 977 StringRef OverloadedSuffix, StringRef IRName, bool IsMasked, in RVVIntrinsic() argument
1040 computeBuiltinTypes(llvm::ArrayRef<PrototypeDescriptor> Prototype,bool IsMasked,bool HasMaskedOffOperand,bool HasVL,unsigned NF,PolicyScheme DefaultScheme,Policy PolicyAttrs,bool IsTuple) computeBuiltinTypes() argument
1144 updateNamesAndPolicy(bool IsMasked,bool HasPolicy,std::string & Name,std::string & BuiltinName,std::string & OverloadedName,Policy & PolicyAttrs,bool HasFRMRoundModeOp) updateNamesAndPolicy() argument
[all...] |
| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVExpandAtomicPseudoInsts.cpp | 390 AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width, in expandAtomicBinOp()
440 AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width, in expandAtomicMinMaxOp()
626 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool IsMasked, in expandAtomicCmpXchg()
|
| H A D | RISCVISelDAGToDAG.cpp | 295 addVectorLoadStoreOperands(SDNode * Node,unsigned Log2SEW,const SDLoc & DL,unsigned CurOp,bool IsMasked,bool IsStridedOrIndexed,SmallVectorImpl<SDValue> & Operands,bool IsLoad,MVT * IndexVT) addVectorLoadStoreOperands() argument
339 selectVLSEG(SDNode * Node,bool IsMasked,bool IsStrided) selectVLSEG() argument
379 selectVLSEGFF(SDNode * Node,bool IsMasked) selectVLSEGFF() argument
421 selectVLXSEG(SDNode * Node,bool IsMasked,bool IsOrdered) selectVLXSEG() argument
472 selectVSSEG(SDNode * Node,bool IsMasked,bool IsStrided) selectVSSEG() argument
504 selectVSXSEG(SDNode * Node,bool IsMasked,bool IsOrdered) selectVSXSEG() argument
1883 bool IsMasked = IntNo == Intrinsic::riscv_vloxei_mask || Select() local
1927 bool IsMasked = IntNo == Intrinsic::riscv_vle_mask || Select() local
1971 bool IsMasked = IntNo == Intrinsic::riscv_vleff_mask; Select() local
2081 bool IsMasked = IntNo == Intrinsic::riscv_vsoxei_mask || Select() local
2125 bool IsMasked = IntNo == Intrinsic::riscv_vse_mask || Select() local
3733 bool IsMasked = false; performCombineVMergeAndVOps() local
[all...] |
| H A D | RISCVISelLowering.cpp | 8827 bool IsMasked = NumOps == 7; lowerVectorIntrinsicScalars() local
|
| /llvm-project/llvm/lib/IR/ |
| H A D | VFABIDemangler.cpp | 59 /// sets `IsMasked` accordingly. If successful, the <mask> token is removed in tryParseMask() argument
389 bool IsMasked; tryDemangleForVFABI() local
|
| /llvm-project/clang/lib/Sema/ |
| H A D | SemaRISCV.cpp | 371 InitRVVIntrinsic(const RVVIntrinsicRecord & Record,StringRef SuffixStr,StringRef OverloadedSuffixStr,bool IsMasked,RVVTypes & Signature,bool HasPolicy,Policy PolicyAttrs) InitRVVIntrinsic() argument
|
| /llvm-project/clang/include/clang/Support/ |
| H A D | RISCVVIntrinsicUtils.h | 389 bool IsMasked; variable
|
| /llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlan.h | 2329 bool IsMasked = false; global() variable
|
| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 18354 getCombineLoadStoreParts(SDNode * N,unsigned Inc,unsigned Dec,bool & IsLoad,bool & IsMasked,SDValue & Ptr,const TargetLowering & TLI) getCombineLoadStoreParts() argument
18406 bool IsMasked = false; CombineToPreIndexedLoadStore() local
18646 bool IsMasked = false; shouldCombineToPostInc() local
18669 getPostIndexedLoadStoreOp(SDNode * N,bool & IsLoad,bool & IsMasked,SDValue & Ptr,SDValue & BasePtr,SDValue & Offset,ISD::MemIndexedMode & AM,SelectionDAG & DAG,const TargetLowering & TLI) getPostIndexedLoadStoreOp() argument
18714 bool IsMasked = false; CombineToPostIndexedLoadStore() local
[all...] |
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4953 bool IsMasked = InMask.getNode() != nullptr; tryVPTESTM() local
|
| H A D | X86ISelLowering.cpp | 25285 bool IsMasked = false; getTargetVShiftNode() local
[all...] |
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 19885 getMVEIndexedAddressParts(SDNode * Ptr,EVT VT,Align Alignment,bool isSEXTLoad,bool IsMasked,bool isLE,SDValue & Base,SDValue & Offset,bool & isInc,SelectionDAG & DAG) getMVEIndexedAddressParts() argument
19952 bool IsMasked = false; getPreIndexedAddressParts() local
20010 bool IsMasked = false; getPostIndexedAddressParts() local
[all...] |
| /llvm-project/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 21773 bool IsMasked = false; EmitRISCVBuiltinExpr() local
|