| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64GlobalISelUtils.cpp | 155 AArch64CC::CondCode &CondCode2, bool &Invert) { in changeVectorFCMPPredToAArch64CC()
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| H A D | AArch64PostLegalizerLowering.cpp | 975 bool Invert = false; in lowerVectorFCMP() local
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| H A D | AArch64InstructionSelector.cpp | 1136 bool Invert) { in emitSelect()
1392 static Register getTestBitReg(Register Reg, uint64_t &Bit, bool &Invert, in getTestBitReg()
1557 MachineInstr &AndInst, bool Invert, MachineBasicBlock *DstMBB, in tryOptAndIntoCompareBranch()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 497 bool Invert = !DefMI; in optimizeSelect() local
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| H A D | LanaiISelLowering.cpp | 1348 bool &Invert, SDValue &OtherOp, in isConditionalZeroOrAllOnes()
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| /openbsd-src/gnu/llvm/llvm/lib/Transforms/Scalar/ |
| H A D | StructurizeCFG.cpp | 453 bool Invert) { in buildCondition()
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| /openbsd-src/gnu/llvm/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombinePHI.cpp | 1332 std::optional<bool> Invert; in simplifyUsingControlFlow() local
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| /openbsd-src/gnu/llvm/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 1169 bool Invert = false; in LowerSETCC() local
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| /openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 1139 bool Invert = !DefMI; in optimizeSelect() local
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| H A D | RISCVISelLowering.cpp | 9959 bool Invert = CCVal == ISD::SETEQ; in combine_CC() local
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| /openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 2951 bool &Invert) { in getVectorComparisonOrInvert()
3034 bool Invert = false; in lowerVectorSETCC() local
6919 bool Invert = false; in combineCCMask() local
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| /openbsd-src/gnu/llvm/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1972 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1); in LowerSETCC() local
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 2974 bool &Invert) { in changeVectorFPCCToAArch64CC()
3728 static SDValue valueToCarryFlag(SDValue Value, SelectionDAG &DAG, bool Invert) { in valueToCarryFlag()
3741 bool Invert) { in carryFlagToValue()
20414 static SDValue getTestBitOperand(SDValue Op, unsigned &Bit, bool &Invert, in getTestBitOperand()
20491 bool Invert = false; in performTBZCombine() local
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| H A D | AArch64ISelDAGToDAG.cpp | 3893 bool Invert) { in SelectSVELogicalImm()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 2361 bool Invert = !DefMI; in optimizeSelect() local
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| H A D | ARMISelLowering.cpp | 6709 bool Invert = false; in LowerVSETCC() local
12353 SDValue &CC, bool &Invert, in isConditionalZeroOrAllOnes()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 4172 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) { in getCRIdxForSetCC()
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| /openbsd-src/gnu/llvm/llvm/lib/Transforms/Utils/ |
| H A D | SimplifyCFG.cpp | 2870 bool Invert = false; in SpeculativelyExecuteBB() local
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 25009 bool Invert = false; in LowerVSETCC() local
25042 bool Invert = Cond == ISD::SETNE || in LowerVSETCC() local
25248 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1); in emitFlagsForSetcc() local
42238 auto GetDemandedMasks = [&](SDValue Op, bool Invert = false) { in SimplifyDemandedVectorEltsForTargetNode()
52633 auto GetDemandedMasks = [&](SDValue Op, bool Invert = false) { in combineAndnp()
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| /openbsd-src/gnu/llvm/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 239 bool Invert = false) { in EmitBinaryAtomicPost()
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