| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64GlobalISelUtils.cpp | 154 AArch64CC::CondCode &CondCode2, bool &Invert) { in changeVectorFCMPPredToAArch64CC()
|
| H A D | AArch64PostLegalizerLowering.cpp | 930 bool Invert; in lowerVectorFCMP() local
|
| H A D | AArch64InstructionSelector.cpp | 1068 bool Invert) { in emitSelect()
1240 static Register getTestBitReg(Register Reg, uint64_t &Bit, bool &Invert, in getTestBitReg()
1397 MachineInstr &AndInst, bool Invert, MachineBasicBlock *DstMBB, in tryOptAndIntoCompareBranch()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 499 bool Invert = !DefMI; in optimizeSelect() local
|
| H A D | LanaiISelLowering.cpp | 1348 bool &Invert, SDValue &OtherOp, in isConditionalZeroOrAllOnes()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| H A D | StructurizeCFG.cpp | 446 bool Invert) { in buildCondition()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 1168 bool Invert = false; in LowerSETCC() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 2766 bool &Invert) { in getVectorComparisonOrInvert()
2849 bool Invert = false; in lowerVectorSETCC() local
6494 bool Invert = false; in combineCCMask() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1932 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1); in LowerSETCC() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 5754 bool Invert = CCVal == ISD::SETEQ; in PerformDAGCombine() local
5809 bool Invert = CCVal == ISD::SETEQ; in PerformDAGCombine() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 3188 bool Invert) { in SelectSVELogicalImm()
|
| H A D | AArch64ISelLowering.cpp | 2347 bool &Invert) { in changeVectorFPCCToAArch64CC()
15286 static SDValue getTestBitOperand(SDValue Op, unsigned &Bit, bool &Invert, in getTestBitOperand()
15363 bool Invert = false; in performTBZCombine() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 2336 bool Invert = !DefMI; in optimizeSelect() local
|
| H A D | ARMISelLowering.cpp | 6429 bool Invert = false; in LowerVSETCC() local
11778 SDValue &CC, bool &Invert, in isConditionalZeroOrAllOnes()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 4144 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) { in getCRIdxForSetCC()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| H A D | SimplifyCFG.cpp | 2368 bool Invert = false; in SpeculativelyExecuteBB() local
|
| /netbsd-src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 202 bool Invert = false) { in EmitBinaryAtomicPost()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 23170 bool Invert = false; in LowerVSETCC() local
23203 bool Invert = Cond == ISD::SETNE || in LowerVSETCC() local
23408 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1); in emitFlagsForSetcc() local
|