| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ExpandImm.cpp | 322 uint64_t Imm2 = MaybeDecomposition->second; in tryOrrOfLogicalImmediates() local
348 uint64_t Imm2 = MaybeDecomposition->second; in tryAndOfLogicalImmediates() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 204 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, in emitII() argument
253 int16_t Imm2, SMLoc IDLoc, in emitRRIII() argument
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 1659 int16_t Imm1 = 0, NewImm1 = 0, Imm2 = 0, NewImm2 = 0; eliminateRedundantCompare() local
|
| H A D | PPCInstrInfo.cpp | 3196 selectReg(int64_t Imm1,int64_t Imm2,unsigned CompareOpc,unsigned TrueReg,unsigned FalseReg,unsigned CRSubReg) selectReg() argument
|
| H A D | PPCISelDAGToDAG.cpp | 5080 unsigned Imm2; tryAsSingleRLWIMI() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 2102 fastEmitInst_rii(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0,uint64_t Imm1,uint64_t Imm2) fastEmitInst_rii() argument
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 2602 bool Imm1 = Src1.isImm(), Imm2 = Src2.isImm(); in evaluateHexCompare2() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 1406 int Imm2 = cast<ConstantSDNode>(Op.getOperand(4))->getSExtValue(); lowerINTRINSIC_VOID() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1568 Register Imm2 = Add2Def->getOperand(2).getReg(); matchPtrAddImmedChain() local
1647 Register Imm2 = Shl2Def->getOperand(2).getReg(); matchShiftImmedChain() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 5327 int64_t Imm1, Imm2; parseModImm() local
|