1 enum { 2 IrqCLOCK = 0, /* legacy external i8259 IRQs */ 3 IrqKBD = 1, 4 IrqUART1 = 3, 5 IrqUART0 = 4, 6 IrqPCMCIA = 5, 7 IrqFLOPPY = 6, 8 IrqLPT = 7, 9 IrqIRQ7 = 7, 10 IrqAUX = 12, /* PS/2 port */ 11 IrqIRQ13 = 13, /* coprocessor on 386 */ 12 IrqATA0 = 14, 13 IrqATA1 = 15, 14 }; 15 16 enum { 17 IdtPIC = 32, /* external i8259 interrupts */ 18 19 IdtLINT0 = 48, /* local APIC interrupts */ 20 IdtLINT1 = 49, 21 IdtTIMER = 50, 22 IdtERROR = 51, 23 IdtPMC = 52, 24 IdtTHS = 53, 25 26 IdtIPI = 62, 27 IdtSPURIOUS = 63, /* end local APIC interrupts */ 28 IdtSYSCALL = 64, /* unused on AMD64 */ 29 IdtIOAPIC = 65, /* IOAPIC interrupts */ 30 31 IdtMAX = 255, /* end IOAPIC interrupts */ 32 }; 33 34 typedef struct Vctl { 35 Vctl* next; /* handlers on this vector */ 36 37 int isintr; /* interrupt or fault/trap */ 38 39 int irq; 40 void (*f)(Ureg*, void*); /* handler to call */ 41 void* a; /* argument to call it with */ 42 int tbdf; 43 char name[KNAMELEN]; /* of driver */ 44 char *type; 45 46 int (*isr)(int); /* get isr bit for this irq */ 47 int (*eoi)(int); /* eoi */ 48 int vno; 49 } Vctl; 50 51 enum { 52 BusCBUS = 0, /* Corollary CBUS */ 53 BusCBUSII, /* Corollary CBUS II */ 54 BusEISA, /* Extended ISA */ 55 BusFUTURE, /* IEEE Futurebus */ 56 BusINTERN, /* Internal bus */ 57 BusISA, /* Industry Standard Architecture */ 58 BusMBI, /* Multibus I */ 59 BusMBII, /* Multibus II */ 60 BusMCA, /* Micro Channel Architecture */ 61 BusMPI, /* MPI */ 62 BusMPSA, /* MPSA */ 63 BusNUBUS, /* Apple Macintosh NuBus */ 64 BusPCI, /* Peripheral Component Interconnect */ 65 BusPCMCIA, /* PC Memory Card International Association */ 66 BusTC, /* DEC TurboChannel */ 67 BusVL, /* VESA Local bus */ 68 BusVME, /* VMEbus */ 69 BusXPRESS, /* Express System Bus */ 70 }; 71 72 #define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8)) 73 #define BUSFNO(tbdf) (((tbdf)>>8)&0x07) 74 #define BUSDNO(tbdf) (((tbdf)>>11)&0x1F) 75 #define BUSBNO(tbdf) (((tbdf)>>16)&0xFF) 76 #define BUSTYPE(tbdf) ((tbdf)>>24) 77 #define BUSBDF(tbdf) ((tbdf)&0x00FFFF00) 78 #define BUSUNKNOWN (-1) 79 80 enum { 81 MaxEISA = 16, 82 CfgEISA = 0xC80, 83 }; 84 85 /* 86 * PCI support code. 87 */ 88 enum { /* type 0 and type 1 pre-defined header */ 89 PciVID = 0x00, /* vendor ID */ 90 PciDID = 0x02, /* device ID */ 91 PciPCR = 0x04, /* command */ 92 PciPSR = 0x06, /* status */ 93 PciRID = 0x08, /* revision ID */ 94 PciCCRp = 0x09, /* programming interface class code */ 95 PciCCRu = 0x0A, /* sub-class code */ 96 PciCCRb = 0x0B, /* base class code */ 97 PciCLS = 0x0C, /* cache line size */ 98 PciLTR = 0x0D, /* latency timer */ 99 PciHDT = 0x0E, /* header type */ 100 PciBST = 0x0F, /* BIST */ 101 102 PciBAR0 = 0x10, /* base address */ 103 PciBAR1 = 0x14, 104 105 PciCP = 0x34, /* capabilities pointer */ 106 107 PciINTL = 0x3C, /* interrupt line */ 108 PciINTP = 0x3D, /* interrupt pin */ 109 }; 110 111 /* ccrb (base class code) values; controller types */ 112 enum { 113 Pcibcpci1 = 0, /* pci 1.0; no class codes defined */ 114 Pcibcstore = 1, /* mass storage */ 115 Pcibcnet = 2, /* network */ 116 Pcibcdisp = 3, /* display */ 117 Pcibcmmedia = 4, /* multimedia */ 118 Pcibcmem = 5, /* memory */ 119 Pcibcbridge = 6, /* bridge */ 120 Pcibccomm = 7, /* simple comms (e.g., serial) */ 121 Pcibcbasesys = 8, /* base system */ 122 Pcibcinput = 9, /* input */ 123 Pcibcdock = 0xa, /* docking stations */ 124 Pcibcproc = 0xb, /* processors */ 125 Pcibcserial = 0xc, /* serial bus (e.g., USB) */ 126 Pcibcwireless = 0xd, /* wireless */ 127 Pcibcintell = 0xe, /* intelligent i/o */ 128 Pcibcsatcom = 0xf, /* satellite comms */ 129 Pcibccrypto = 0x10, /* encryption/decryption */ 130 Pcibcdacq = 0x11, /* data acquisition & signal proc. */ 131 }; 132 133 /* ccru (sub-class code) values; common cases only */ 134 enum { 135 /* mass storage */ 136 Pciscscsi = 0, /* SCSI */ 137 Pciscide = 1, /* IDE (ATA) */ 138 Pciscsata = 6, /* SATA */ 139 140 /* network */ 141 Pciscether = 0, /* Ethernet */ 142 143 /* display */ 144 Pciscvga = 0, /* VGA */ 145 Pciscxga = 1, /* XGA */ 146 Pcisc3d = 2, /* 3D */ 147 148 /* bridges */ 149 Pcischostpci = 0, /* host/pci */ 150 Pciscpcicpci = 1, /* pci/pci */ 151 152 /* simple comms */ 153 Pciscserial = 0, /* 16450, etc. */ 154 Pciscmultiser = 1, /* multiport serial */ 155 156 /* serial bus */ 157 Pciscusb = 3, /* USB */ 158 }; 159 160 enum { /* type 0 pre-defined header */ 161 PciCIS = 0x28, /* cardbus CIS pointer */ 162 PciSVID = 0x2C, /* subsystem vendor ID */ 163 PciSID = 0x2E, /* cardbus CIS pointer */ 164 PciEBAR0 = 0x30, /* expansion ROM base address */ 165 PciMGNT = 0x3E, /* burst period length */ 166 PciMLT = 0x3F, /* maximum latency between bursts */ 167 }; 168 169 enum { /* type 1 pre-defined header */ 170 PciPBN = 0x18, /* primary bus number */ 171 PciSBN = 0x19, /* secondary bus number */ 172 PciUBN = 0x1A, /* subordinate bus number */ 173 PciSLTR = 0x1B, /* secondary latency timer */ 174 PciIBR = 0x1C, /* I/O base */ 175 PciILR = 0x1D, /* I/O limit */ 176 PciSPSR = 0x1E, /* secondary status */ 177 PciMBR = 0x20, /* memory base */ 178 PciMLR = 0x22, /* memory limit */ 179 PciPMBR = 0x24, /* prefetchable memory base */ 180 PciPMLR = 0x26, /* prefetchable memory limit */ 181 PciPUBR = 0x28, /* prefetchable base upper 32 bits */ 182 PciPULR = 0x2C, /* prefetchable limit upper 32 bits */ 183 PciIUBR = 0x30, /* I/O base upper 16 bits */ 184 PciIULR = 0x32, /* I/O limit upper 16 bits */ 185 PciEBAR1 = 0x28, /* expansion ROM base address */ 186 PciBCR = 0x3E, /* bridge control register */ 187 }; 188 189 enum { /* type 2 pre-defined header */ 190 PciCBExCA = 0x10, 191 PciCBSPSR = 0x16, 192 PciCBPBN = 0x18, /* primary bus number */ 193 PciCBSBN = 0x19, /* secondary bus number */ 194 PciCBUBN = 0x1A, /* subordinate bus number */ 195 PciCBSLTR = 0x1B, /* secondary latency timer */ 196 PciCBMBR0 = 0x1C, 197 PciCBMLR0 = 0x20, 198 PciCBMBR1 = 0x24, 199 PciCBMLR1 = 0x28, 200 PciCBIBR0 = 0x2C, /* I/O base */ 201 PciCBILR0 = 0x30, /* I/O limit */ 202 PciCBIBR1 = 0x34, /* I/O base */ 203 PciCBILR1 = 0x38, /* I/O limit */ 204 PciCBSVID = 0x40, /* subsystem vendor ID */ 205 PciCBSID = 0x42, /* subsystem ID */ 206 PciCBLMBAR = 0x44, /* legacy mode base address */ 207 }; 208 209 /* capabilities */ 210 enum { 211 PciCapPMG = 0x01, /* power management */ 212 PciCapAGP = 0x02, 213 PciCapVPD = 0x03, /* vital product data */ 214 PciCapSID = 0x04, /* slot id */ 215 PciCapMSI = 0x05, 216 PciCapCHS = 0x06, /* compact pci hot swap */ 217 PciCapPCIX = 0x07, 218 PciCapHTC = 0x08, /* hypertransport irq conf */ 219 PciCapVND = 0x09, /* vendor specific information */ 220 PciCapPCIe = 0x10, 221 PciCapMSIX = 0x11, 222 PciCapSATA = 0x12, 223 PciCapHSW = 0x0c, /* hot swap */ 224 }; 225 226 typedef struct Pcisiz Pcisiz; 227 struct Pcisiz 228 { 229 Pcidev* dev; 230 int siz; 231 int bar; 232 }; 233 234 typedef struct Pcidev Pcidev; 235 struct Pcidev 236 { 237 int tbdf; /* type+bus+device+function */ 238 ushort vid; /* vendor ID */ 239 ushort did; /* device ID */ 240 241 ushort pcr; 242 243 uchar rid; 244 uchar ccrp; 245 uchar ccru; 246 uchar ccrb; 247 uchar cls; 248 uchar ltr; 249 250 struct { 251 ulong bar; /* base address */ 252 int size; 253 } mem[6]; 254 255 struct { 256 ulong bar; 257 int size; 258 } rom; 259 uchar intl; /* interrupt line */ 260 261 Pcidev* list; 262 Pcidev* link; /* next device on this bno */ 263 264 Pcidev* bridge; /* down a bus */ 265 struct { 266 ulong bar; 267 int size; 268 } ioa, mema; 269 270 int pmrb; /* power management register block */ 271 }; 272 273 #define PCIWINDOW 0 274 #define PCIWADDR64(va) (PADDR(va)+PCIWINDOW) 275 #define PCIWADDR32(va) ((ulong)PCIWADDR64(va)) 276 #define ISAWINDOW 0 277 #define ISAWADDR(va) (PADDR(va)+ISAWINDOW) 278 #define PCIWADDRL(va) ((ulong)PCIWADDR64(va)) 279 #define PCIWADDRH(va) ((ulong)(PCIWADDR64(va)>>32)) 280