1 enum { 2 BusCBUS = 0, /* Corollary CBUS */ 3 BusCBUSII, /* Corollary CBUS II */ 4 BusEISA, /* Extended ISA */ 5 BusFUTURE, /* IEEE Futurebus */ 6 BusINTERN, /* Internal bus */ 7 BusISA, /* Industry Standard Architecture */ 8 BusMBI, /* Multibus I */ 9 BusMBII, /* Multibus II */ 10 BusMCA, /* Micro Channel Architecture */ 11 BusMPI, /* MPI */ 12 BusMPSA, /* MPSA */ 13 BusNUBUS, /* Apple Macintosh NuBus */ 14 BusPCI, /* Peripheral Component Interconnect */ 15 BusPCMCIA, /* PC Memory Card International Association */ 16 BusTC, /* DEC TurboChannel */ 17 BusVL, /* VESA Local bus */ 18 BusVME, /* VMEbus */ 19 BusXPRESS, /* Express System Bus */ 20 BUSUNKNOWN = -1 21 }; 22 23 #define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8)) 24 #define BUSFNO(tbdf) (((tbdf)>>8)&0x07) 25 #define BUSDNO(tbdf) (((tbdf)>>11)&0x1F) 26 #define BUSBNO(tbdf) (((tbdf)>>16)&0xFF) 27 #define BUSTYPE(tbdf) ((tbdf)>>24) 28 #define BUSBDF(tbdf) ((tbdf)&0x00FFFF00) 29 30 /* 31 * PCI support code. 32 */ 33 enum { /* type 0 & type 1 pre-defined header */ 34 PciVID = 0x00, /* vendor ID */ 35 PciDID = 0x02, /* device ID */ 36 PciPCR = 0x04, /* command */ 37 PciPSR = 0x06, /* status */ 38 PciRID = 0x08, /* revision ID */ 39 PciCCRp = 0x09, /* programming interface class code */ 40 PciCCRu = 0x0A, /* sub-class code */ 41 PciCCRb = 0x0B, /* base class code */ 42 PciCLS = 0x0C, /* cache line size */ 43 PciLTR = 0x0D, /* latency timer */ 44 PciHDT = 0x0E, /* header type */ 45 PciBST = 0x0F, /* BIST */ 46 }; 47 48 /* ccrb (base class code) values; controller types */ 49 enum { 50 Pcibcpci1 = 0, /* pci 1.0; no class codes defined */ 51 Pcibcstore = 1, /* mass storage */ 52 Pcibcnet = 2, /* network */ 53 Pcibcdisp = 3, /* display */ 54 Pcibcmmedia = 4, /* multimedia */ 55 Pcibcmem = 5, /* memory */ 56 Pcibcbridge = 6, /* bridge */ 57 Pcibccomm = 7, /* simple comms (e.g., serial) */ 58 Pcibcbasesys = 8, /* base system */ 59 Pcibcinput = 9, /* input */ 60 Pcibcdock = 0xa, /* docking stations */ 61 Pcibcproc = 0xb, /* processors */ 62 Pcibcserial = 0xc, /* serial bus (e.g., USB) */ 63 Pcibcwireless = 0xd, /* wireless */ 64 Pcibcintell = 0xe, /* intelligent i/o */ 65 Pcibcsatcom = 0xf, /* satellite comms */ 66 Pcibccrypto = 0x10, /* encryption/decryption */ 67 Pcibcdacq = 0x11, /* data acquisition & signal proc. */ 68 }; 69 70 /* ccru (sub-class code) values; common cases only */ 71 enum { 72 /* mass storage */ 73 Pciscscsi = 0, /* SCSI */ 74 Pciscide = 1, /* IDE (ATA) */ 75 76 /* network */ 77 Pciscether = 0, /* Ethernet */ 78 79 /* display */ 80 Pciscvga = 0, /* VGA */ 81 Pciscxga = 1, /* XGA */ 82 Pcisc3d = 2, /* 3D */ 83 84 /* bridges */ 85 Pcischostpci = 0, /* host/pci */ 86 Pciscpcicpci = 1, /* pci/pci */ 87 88 /* simple comms */ 89 Pciscserial = 0, /* 16450, etc. */ 90 Pciscmultiser = 1, /* multiport serial */ 91 92 /* serial bus */ 93 Pciscusb = 3, /* USB */ 94 }; 95 96 enum { /* type 0 pre-defined header */ 97 PciCIS = 0x28, /* cardbus CIS pointer */ 98 PciSVID = 0x2C, /* subsystem vendor ID */ 99 PciSID = 0x2E, /* cardbus CIS pointer */ 100 PciEBAR0 = 0x30, /* expansion ROM base address */ 101 PciMGNT = 0x3E, /* burst period length */ 102 PciMLT = 0x3F, /* maximum latency between bursts */ 103 }; 104 105 enum { /* type 1 pre-defined header */ 106 PciPBN = 0x18, /* primary bus number */ 107 PciSBN = 0x19, /* secondary bus number */ 108 PciUBN = 0x1A, /* subordinate bus number */ 109 PciSLTR = 0x1B, /* secondary latency timer */ 110 PciIBR = 0x1C, /* I/O base */ 111 PciILR = 0x1D, /* I/O limit */ 112 PciSPSR = 0x1E, /* secondary status */ 113 PciMBR = 0x20, /* memory base */ 114 PciMLR = 0x22, /* memory limit */ 115 PciPMBR = 0x24, /* prefetchable memory base */ 116 PciPMLR = 0x26, /* prefetchable memory limit */ 117 PciPUBR = 0x28, /* prefetchable base upper 32 bits */ 118 PciPULR = 0x2C, /* prefetchable limit upper 32 bits */ 119 PciIUBR = 0x30, /* I/O base upper 16 bits */ 120 PciIULR = 0x32, /* I/O limit upper 16 bits */ 121 PciEBAR1 = 0x28, /* expansion ROM base address */ 122 PciBCR = 0x3E, /* bridge control register */ 123 }; 124 125 enum { /* type 2 pre-defined header */ 126 PciCBExCA = 0x10, 127 PciCBSPSR = 0x16, 128 PciCBPBN = 0x18, /* primary bus number */ 129 PciCBSBN = 0x19, /* secondary bus number */ 130 PciCBUBN = 0x1A, /* subordinate bus number */ 131 PciCBSLTR = 0x1B, /* secondary latency timer */ 132 PciCBMBR0 = 0x1C, 133 PciCBMLR0 = 0x20, 134 PciCBMBR1 = 0x24, 135 PciCBMLR1 = 0x28, 136 PciCBIBR0 = 0x2C, /* I/O base */ 137 PciCBILR0 = 0x30, /* I/O limit */ 138 PciCBIBR1 = 0x34, /* I/O base */ 139 PciCBILR1 = 0x38, /* I/O limit */ 140 PciCBSVID = 0x40, /* subsystem vendor ID */ 141 PciCBSID = 0x42, /* subsystem ID */ 142 PciCBLMBAR = 0x44, /* legacy mode base address */ 143 }; 144 145 typedef struct Pcisiz Pcisiz; 146 struct Pcisiz 147 { 148 Pcidev* dev; 149 int siz; 150 int bar; 151 }; 152 153 typedef struct Pcidev Pcidev; 154 struct Pcidev 155 { 156 int tbdf; /* type+bus+device+function */ 157 ushort vid; /* vendor ID */ 158 ushort did; /* device ID */ 159 160 ushort pcr; 161 162 uchar rid; 163 uchar ccrp; 164 uchar ccru; 165 uchar ccrb; 166 uchar cls; 167 uchar ltr; 168 169 struct { 170 ulong bar; /* base address */ 171 int size; 172 } mem[6]; 173 174 struct { 175 ulong bar; 176 int size; 177 } rom; 178 uchar intl; /* interrupt line */ 179 180 Pcidev* list; 181 Pcidev* link; /* next device on this bno */ 182 183 Pcidev* bridge; /* down a bus */ 184 struct { 185 ulong bar; 186 int size; 187 } ioa, mema; 188 189 int pmrb; /* power management register block */ 190 }; 191 192 #define PCIWINDOW 0 193 #define PCIWADDR(va) (PADDR(va)+PCIWINDOW) 194 195 /* 196 * Kirkwood stuff 197 */ 198 199 enum { 200 AddrEfuse = PHYSIO+0x1008c, 201 Addrpci = PHYSIO+0x40000, /* for registers below */ 202 Addrpcibase = PHYSIO+0x41800, /* for registers below */ 203 AddrMpp = PHYSIO+0x10000, 204 AddrSdio = PHYSIO+0x90000, 205 }; 206 207 enum { 208 Socrevz0, 209 Socreva0 = 2, 210 Socreva1, 211 }; 212 213 enum { 214 /* registers; if we actually use these, change to soc.pci(base)->reg */ 215 PciBAR0 = Addrpcibase + 4, /* base address */ 216 PciBAR1 = Addrpcibase + 8, 217 218 PciCP = Addrpci + 0x64, /* capabilities pointer */ 219 220 PciINTL = Addrpci + 0x3c, /* interrupt line */ 221 PciINTP = PciINTL + 1, /* interrupt pin */ 222 }; 223 224 /* 225 * interrupt stuff 226 */ 227 228 enum { 229 Irqlo, Irqhi, Irqbridge, 230 }; 231 232 enum { 233 /* main interrupt cause low register bit #s (LE) */ 234 IRQ0hisum, /* summary of main intr high cause reg */ 235 IRQ0bridge, 236 IRQ0h2cdoorbell, 237 IRQ0c2hdoorbell, 238 _IRQ0reserved0, 239 IRQ0xor0chan0, 240 IRQ0xor0chan1, 241 IRQ0xor1chan0, 242 IRQ0xor1chan1, 243 IRQ0pex0int, /* pex = pci-express */ 244 _IRQ0reserved1, 245 IRQ0gbe0sum, 246 IRQ0gbe0rx, 247 IRQ0gbe0tx, 248 IRQ0gbe0misc, 249 IRQ0gbe1sum, 250 IRQ0gbe1rx, 251 IRQ0gbe1tx, 252 IRQ0gbe1misc, 253 IRQ0usb0, 254 _IRQ0reserved2, 255 IRQ0sata, 256 IRQ0crypto, 257 IRQ0spi, 258 IRQ0audio, 259 _IRQ0reserved3, 260 IRQ0ts0, 261 _IRQ0reserved4, 262 IRQ0sdio, 263 IRQ0twsi, 264 IRQ0avb, 265 IRQ0tdm, 266 267 /* main interrupt cause high register bit #s (LE) */ 268 _IRQ1reserved0 = 0, 269 IRQ1uart0, 270 IRQ1uart1, 271 IRQ1gpiolo0, 272 IRQ1gpiolo1, 273 IRQ1gpiolo2, 274 IRQ1gpiolo3, 275 IRQ1gpiohi0, 276 IRQ1gpiohi1, 277 IRQ1gpiohi2, 278 IRQ1gpiohi3, 279 IRQ1xor0err, 280 IRQ1xor1err, 281 IRQ1pex0err, 282 _IRQ1reserved1, 283 IRQ1gbe0err, 284 IRQ1gbe1err, 285 IRQ1usberr, 286 IRQ1cryptoerr, 287 IRQ1audioerr, 288 _IRQ1reserved2, 289 _IRQ1reserved3, 290 IRQ1rtc, 291 292 /* bridged-interrupt causes */ 293 IRQcpuself = 0, 294 IRQcputimer0, 295 IRQcputimer1, 296 IRQcputimerwd, 297 IRQaccesserr, 298 }; 299 300 /* 301 * interrupt controller 302 */ 303 typedef struct IntrReg IntrReg; 304 struct IntrReg 305 { 306 struct { 307 ulong irq; /* main intr cause reg (ro) */ 308 ulong irqmask; 309 ulong fiqmask; 310 ulong epmask; 311 } lo, hi; 312 }; 313 314 /* 315 * CPU control & status (archkw.c and trap.c) 316 */ 317 typedef struct CpucsReg CpucsReg; 318 struct CpucsReg 319 { 320 ulong cpucfg; 321 ulong cpucsr; 322 ulong rstout; 323 ulong softreset; 324 ulong irq; /* mbus(-l) bridge interrupt cause */ 325 ulong irqmask; /* ⋯ mask */ 326 ulong mempm; /* memory power mgmt. control */ 327 ulong clockgate; /* clock enable bits */ 328 ulong biu; 329 ulong pad0; 330 ulong l2cfg; /* turn l2 cache on or off, set coherency */ 331 ulong pad1[2]; 332 ulong l2tm0; 333 ulong l2tm1; 334 ulong pad2[2]; 335 ulong l2pm; 336 ulong ram0; 337 ulong ram1; 338 ulong ram2; 339 ulong ram3; 340 }; 341 342 enum { 343 /* cpucfg bits */ 344 Cfgvecinithi = 1<<1, /* boot at 0xffff0000, not 0; default 1 */ 345 Cfgbigendreset = 3<<1, /* init. as big-endian at reset; default 0 */ 346 Cfgiprefetch = 1<<16, /* instruction prefetch enable */ 347 Cfgdprefetch = 1<<17, /* data prefetch enable */ 348 349 /* cpucsr bits */ 350 Reset = 1<<1, /* reset cpu core */ 351 352 /* rstout bits */ 353 RstoutPex = 1<<0, /* assert RSTOUTn at pci-e reset */ 354 RstoutWatchdog = 1<<1, /* assert RSTOUTn at watchdog timeout */ 355 RstoutSoft = 1<<2, /* assert RSTOUTn at sw reset */ 356 357 /* softreset bits */ 358 ResetSystem = 1<<0, /* assert RSTOUTn pin on SoftRstOutEn */ 359 360 /* l2cfg bits */ 361 L2ecc = 1<<2, 362 L2exists = 1<<3, /* l2 cache doesn't ignore cpu */ 363 L2writethru = 1<<4, /* always WT, else see PTE C & B */ 364 }; 365 366 enum { 367 /* from 88f6281 func'l specs (MV-S104860-00), tables 2 & 3, chapter 2 */ 368 Targdram = 0, /* ddr sdram */ 369 Targflash = 1, 370 Targcesasram = 3, /* security accelerator sram */ 371 372 /* attributes */ 373 Attrcs0 = 0xe, /* chip select 0 (low dram) */ 374 Attrcs1 = 0xd, /* chip select 1 (high dram) */ 375 Attrbootrom = 0x1d, 376 Attrspi = 0x1e, 377 Attrnand = 0x2f, 378 379 Winenable = 1<<0, 380 }; 381 382 typedef struct Pciex Pciex; 383 struct Pciex { 384 ushort venid; /* 0x11ab means Marvell */ 385 ushort devid; /* 0x6281 means 6281 */ 386 ulong csr; 387 ulong revid; 388 ulong bistcache; /* bist hdr type & cache-line size */ 389 ulong bar0; 390 ulong bar0hi; 391 ulong bar1; 392 ulong bar1hi; 393 ulong bar2; 394 ulong bar2hi; 395 ulong _pad0; 396 ushort ssvenid; /* 0x11ab means Marvell */ 397 ushort ssdevid; /* 0x11ab means Marvell */ 398 ulong rombar; 399 ulong caplist; 400 ulong _pad1; 401 ulong intrpinline; /* interrupt pin & line */ 402 ulong pmcap; /* power mgmt. capability header */ 403 ulong pmcsr; /* power mgmt. control & status */ 404 ulong _pad2[2]; 405 ulong msictl; /* msi message control */ 406 ulong msiaddr; 407 ulong msiaddrhi; 408 ulong msidata; 409 ulong cap; 410 ulong devcap; 411 ulong devcsr; 412 ulong linkcap; 413 ulong linkcsr; 414 415 uchar _pad[0x40100-0x40074]; 416 ulong errrep; /* advanced error report header */ 417 ulong uncorrerr; /* uncorrectable error status */ 418 ulong uncorrerrmask; /* uncorrectable error mask */ 419 ulong uncorrerrsev; /* uncorrectable error severity */ 420 ulong correrr; /* correctable error status */ 421 ulong correrrmask; /* correctable error mask */ 422 ulong errcap; /* advanced error capability & ctl. */ 423 ulong hdrlog[4]; /* header log */ 424 /* continues with more rubbish at 0x41a00. some day... */ 425 }; 426