1 /* $NetBSD: bcm53xx_intr.h,v 1.2 2013/10/28 22:51:16 matt Exp $ */ 2 /*- 3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef _ARM_BROADCOM_BCM53XX_INTR_H_ 32 #define _ARM_BROADCOM_BCM53XX_INTR_H_ 33 34 #ifdef _KERNEL_OPT 35 #include "opt_broadcom.h" 36 #endif 37 38 #define PIC_MAXSOURCES 256 39 #define PIC_MAXMAXSOURCES 280 40 41 /* 42 * The BCM53xx uses a generic interrupt controller so pull that stuff. 43 */ 44 #include <arm/cortex/gic_intr.h> 45 #include <arm/cortex/a9tmr_intr.h> /* A9 Timer PPIs */ 46 47 #define IRQ_L2CC 32 48 #define IRQ_PWRWDOG 33 49 #define IRQ_TRAP8 34 50 #define IRQ_TRAP1 35 51 #define IRQ_COMMTX 36 52 #define IRQ__RSVD37 37 53 #define IRQ_COMMRX 38 54 #define IRQ__RSVD39 39 55 #define IRQ_PMU 40 56 #define IRQ__RSVD41 41 57 #define IRQ_CTI 42 58 #define IRQ__RSVD43 43 59 #define IRQ_DEFLAG_CPU0 44 60 #define IRQ_DEFLAG_CPU1 45 61 #define IRQ_ARMCORE_M1_PINS_BUS 46 62 #define IRQ_PCIE0_M0_PINS_BUS 47 63 #define IRQ_PCIE1_M0_PINS_BUS 48 64 #define IRQ_PCIE2_M0_PINS_BUS 49 65 #define IRQ_DMA_M0_PINS_BUS 50 66 #define IRQ_AMAC_M0_PINS_BUS 51 67 #define IRQ_AMAC_M1_PINS_BUS 52 68 #define IRQ_AMAC_M2_PINS_BUS 53 69 #define IRQ_AMAC_M3_PINS_BUS 54 70 #define IRQ_USBH_M0_PINS_BUS 55 71 #define IRQ_USBH_M1_PINS_BUS 56 72 #define IRQ_SDIO_M0_PINS_BUS 57 73 #define IRQ_I2S_M0_PINS_BUS 58 74 #define IRQ_A9JTAG_M0_PINS_BUS 59 75 #define IRQ_JTAG_M0_PINS_BUS 60 76 #define IRQ_ARMCORE_ACP_PINS_BUS 61 77 #define IRQ_ARMCORE_S0_PINS_BUS 62 78 #define IRQ_DDR_S1_PINS_BUS 63 79 #define IRQ_DDR_S2_PINS_BUS 64 80 #define IRQ_PCIE0_S0_PINS_BUS 65 81 #define IRQ_PCIE1_S0_PINS_BUS 66 82 #define IRQ_PCIE2_S0_PINS_BUS 67 83 #define IRQ_ROM_S0_PINS_BUS 68 84 #define IRQ_NAND_S0_PINS_BUS 69 85 #define IRQ_QSPI_S0_PINS_BUS 70 86 #define IRQ_A9JTAG_S0_PINS_BUS 71 87 #define IRQ_APBX_S0_PINS_BUS 72 88 89 #ifdef BCM5301X 90 #define BCM53XXX_IRQ(a,c) ((a)) 91 #elif defined(BCM563XX) 92 #define BCM53XXX_IRQ(a,c) ((a) + (c)) 93 #else 94 #error unknown iProc variant 95 #endif 96 97 #define IRQ_DS_0_PINS_BUS BCM53XXX_IRQ(73, 6) 98 #define IRQ_DS_1_PINS_BUS BCM53XXX_IRQ(74, 6) 99 #define IRQ_DS_2_PINS_BUS BCM53XXX_IRQ(75, 6) 100 #define IRQ_DS_3_PINS_BUS BCM53XXX_IRQ(76, 6) 101 #define IRQ_DS_4_PINS_BUS BCM53XXX_IRQ(77, 6) 102 #define IRQ_DDR_CONTROLLER BCM53XXX_IRQ(78, 6) 103 #define IRQ_DMAC BCM53XXX_IRQ(79, 6) /* 16 */ 104 #define IRQ_DMAC_ABORT BCM53XXX_IRQ(95, 6) 105 #define IRQ_NAND_RD_MISS BCM53XXX_IRQ(96, 6) 106 #define IRQ_NAND_BLK_ERASE_COMP BCM53XXX_IRQ(97, 6) 107 #define IRQ_NAND_COPY_BACK_COMP BCM53XXX_IRQ(98, 6) 108 #define IRQ_NAND_PGM_PAGE_COMP BCM53XXX_IRQ(99, 6) 109 #define IRQ_NAND_RO_CTLR_READY BCM53XXX_IRQ(100, 6) 110 #define IRQ_NAND_RB_B BCM53XXX_IRQ(101, 6) 111 #define IRQ_NAND_ECC_MIPS_UNCORR BCM53XXX_IRQ(102, 6) 112 #define IRQ_NAND_ECC_MIPS_CORR BCM53XXX_IRQ(103, 6) 113 114 #define IRQ_SPI_FULLNESS_REACHED BCM53XXX_IRQ(104, 6) 115 #define IRQ_SPI_TRUNCATED BCM53XXX_IRQ(105, 6) 116 #define IRQ_SPI_IMPATIENT BCM53XXX_IRQ(106, 6) 117 #define IRQ_SPI_SESSION_DONE BCM53XXX_IRQ(107, 6) 118 #define IRQ_SPI_INTERRUPT_OVERREAD BCM53XXX_IRQ(108, 6) 119 #define IRQ_SPI_MSPI_INTERRUPT_DONE BCM53XXX_IRQ(109, 6) 120 #define IRQ_SPI_MSPI_INTERRUPT_HALT_SET_TRANSACTION_DONE \ 121 BCM53XXX_IRQ(110, 6) 122 #define IRQ_USB2 BCM53XXX_IRQ(111, 6) 123 124 #define IRQ_CCA BCM53XXX_IRQ(117, 6) 125 #define IRQ_UART2 BCM53XXX_IRQ(118, 6) 126 #define IRQ_GPIO BCM53XXX_IRQ(119, 6) 127 #define IRQ_I2S BCM53XXX_IRQ(120, 6) 128 #define IRQ_SMBUS1 BCM53XXX_IRQ(121, 6) 129 #define IRQ_TIMER0_1 BCM53XXX_IRQ(122, 7) 130 #define IRQ_TIMER0_2 BCM53XXX_IRQ(123, 7) 131 #define IRQ_TIMER1_1 BCM53XXX_IRQ(124, 7) 132 #define IRQ_TIMER1_2 BCM53XXX_IRQ(125, 7) 133 #define IRQ_RNG BCM53XXX_IRQ(126, 7) 134 #define IRQ_SWITCH_SOC BCM53XXX_IRQ(127, 7) /* 32 */ 135 #define IRQ_NETWORK_LINK_EVENT BCM53XXX_IRQ(127, 7) /* 8 */ 136 #define IRQ_PHY BCM53XXX_IRQ(135, 7) 137 #define IRQ_TIMESYNC BCM53XXX_IRQ(136, 7) 138 #define IRQ_IMP_SLEEP_TIMER BCM53XXX_IRQ(137, 7) /* 3 */ 139 #define IRQ_PCIE_INT0 BCM53XXX_IRQ(159, 55) /* 6 */ 140 #define IRQ_PCIE_INT1 BCM53XXX_IRQ(165, 55) /* 6 */ 141 #define IRQ_PCIE_INT2 BCM53XXX_IRQ(171, 55) /* 6 */ 142 #define IRQ_SDIO BCM53XXX_IRQ(177, 55) 143 #define IRQ_GMAC0 BCM53XXX_IRQ(179, 55) 144 #define IRQ_GMAC1 BCM53XXX_IRQ(180, 55) 145 146 #ifdef BCM5301X 147 #define IRQ_XHCI_0 (112) 148 #define IRQ_XHCI_1 (113) 149 #define IRQ_XHCI_2 (114) 150 #define IRQ_XHCI_3 (115) 151 #define IRQ_XHCI_HSE (116) 152 #define IRQ_FA (178) 153 #define IRQ_GMAC2 (181) 154 #define IRQ_GMAC3 (182) 155 #endif 156 157 #ifdef BCM563XX 158 #define IRQ_SATA_PINS_BUS (73) 159 #define IRQ_SRAM_PINS_BUS (74) 160 #define IRQ_APBW_PINS_BUS (75) 161 #define IRQ_APBX_PINS_BUS (76) 162 #define IRQ_APBY_PINS_BUS (77) 163 #define IRQ_APBZ_PINS_BUS (78) 164 #define IRQ_SMBUS2 (128) 165 #define IRQ_SATA0 (190) 166 #define IRQ_SATA1 (191) 167 #define IRQ_I2S_INTR (201) 168 #define IRQ_MACSEC0 (202) 169 #define IRQ_MACSEC1 (203) 170 #define IRQ_USB2D (238) 171 #define IRQ_APBV_PINS_BUS (239) 172 #define IRQ_SRAM_MEM_CORRECTABLE (240) 173 #define IRQ_SRAM_MEM_UNCORRECTABLE (241) 174 #define IRQ_SRAM_MEM_ACCESS_VIO (242) 175 #define IRQ_SRAM_MEM_SBMA_MISMATCH (243) 176 #define IRQ_CCB_WDT (244) 177 #endif /* BCM563XX */ 178 179 #endif /* _ARM_BROADCOM_BC53XX_INTR_H_ */ 180