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/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp406 isLegalUpTo(const std::vector<std::vector<std::pair<int,unsigned>>> & IGSrcs,const std::vector<R600InstrInfo::BankSwizzle> & Swz,const std::vector<std::pair<int,unsigned>> & TransSrcs,R600InstrInfo::BankSwizzle TransSwz) const isLegalUpTo() argument
475 FindSwizzleForVectorSlot(const std::vector<std::vector<std::pair<int,unsigned>>> & IGSrcs,std::vector<R600InstrInfo::BankSwizzle> & SwzCandidate,const std::vector<std::pair<int,unsigned>> & TransSrcs,R600InstrInfo::BankSwizzle TransSwz) const FindSwizzleForVectorSlot() argument
518 std::vector<std::vector<std::pair<int, unsigned>>> IGSrcs; fitsReadPortLimitations() local
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