/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.cpp | 287 const HexagonRegisterInfo &HRI) { in needsStackFrame() argument 413 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in findShrunkPrologEpilog() local 513 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in emitPrologue() local 597 auto &HRI = *HST.getRegisterInfo(); insertPrologueInBlock() local 770 auto &HRI = *HST.getRegisterInfo(); insertEpilogueInBlock() local 892 auto &HRI = *HST.getRegisterInfo(); insertAllocframe() local 1038 auto &HRI = *HST.getRegisterInfo(); insertCFIInstructionsAt() local 1150 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); hasFP() local 1267 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); getFrameIndexReference() local 1362 insertCSRSpillsInBlock(MachineBasicBlock & MBB,const CSIVect & CSI,const HexagonRegisterInfo & HRI,bool & PrologueStubs) const insertCSRSpillsInBlock() argument 1528 needToReserveScavengingSpillSlots(MachineFunction & MF,const HexagonRegisterInfo & HRI,const TargetRegisterClass * RC) needToReserveScavengingSpillSlots() argument 1831 auto *HRI = B.getParent()->getSubtarget<HexagonSubtarget>().getRegisterInfo(); expandStoreVecPred() local 1862 auto *HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); expandLoadVecPred() local 1881 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); expandStoreVec2() local 1941 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); expandLoadVec2() local 1986 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); expandStoreVec() local 2015 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); expandLoadVec() local 2081 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); determineCalleeSaves() local 2139 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); findPhysReg() local 2170 auto &HRI = *HST.getRegisterInfo(); optimizeSpillSlots() local [all...] |
H A D | HexagonISelDAGToDAG.h | 31 const HexagonRegisterInfo *HRI; variable
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H A D | HexagonVLIWPacketizer.h | 77 const HexagonRegisterInfo *HRI; variable
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H A D | HexagonBranchRelaxation.cpp | 70 const HexagonRegisterInfo *HRI; member
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H A D | HexagonVExtract.cpp | 104 const auto &HRI = *HST->getRegisterInfo(); in runOnMachineFunction() local
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H A D | HexagonConstExtenders.cpp | 384 const HexagonRegisterInfo *HRI = nullptr; member 448 const HexagonRegisterInfo &HRI; member 464 const HexagonRegisterInfo &HRI; member 482 const HexagonRegisterInfo &HRI; member 497 const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); operator <<() local 553 const HexagonRegisterInfo &HRI; global() member [all...] |
H A D | HexagonRDFOpt.cpp | 308 const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in runOnMachineFunction() local
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H A D | HexagonBitSimplify.cpp | 468 auto &HRI = static_cast<const HexagonRegisterInfo&>( in parseRegSequence() local 932 auto &HRI = static_cast<const HexagonRegisterInfo&>( in getFinalVRegClass() local 1098 const HexagonRegisterInfo &HRI; member in __anon2464e5480511::RedundantInstrElimination 1545 const HexagonRegisterInfo &HRI; global() member in __anon2464e5480711::CopyGeneration 1565 const HexagonRegisterInfo &HRI; global() member in __anon2464e5480711::CopyPropagation 1820 const HexagonRegisterInfo &HRI; global() member in __anon2464e5480811::BitSimplification 2800 auto &HRI = *HST.getRegisterInfo(); runOnMachineFunction() local 2937 const HexagonRegisterInfo *HRI = nullptr; global() member in __anon2464e5480d11::HexagonLoopRescheduling [all...] |
H A D | HexagonInstrInfo.cpp | 137 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi)); in isDblRegForSubInst() argument 861 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); copyPhysReg() local 1056 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); expandPostRAPseudo() local 1733 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); ClobbersPredicate() local 2214 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); isDependent() local 3926 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); getDuplexCandidateGroup() local 4330 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); getOperandLatency() local 4501 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); getMemAccessSize() local [all...] |
H A D | HexagonBitTracker.cpp | 136 bool IsSubHi = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi)); in composeWithSubRegIndex() local 95 const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI); mask() local
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H A D | HexagonGenMux.cpp | 89 const HexagonRegisterInfo *HRI = nullptr; global() member in __anon35b8e6b00111::HexagonGenMux
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H A D | HexagonISelLowering.cpp | 460 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); LowerCall() local 667 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); LowerINLINEASM() local 1187 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); LowerRETURNADDR() local 1213 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); LowerFRAMEADDR() local 1313 const auto &HRI = *Subtarget.getRegisterInfo(); GetDynamicTLSAddr() local 1455 auto &HRI = *Subtarget.getRegisterInfo(); HexagonTargetLowering() local [all...] |
H A D | HexagonAsmPrinter.cpp | 271 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); HexagonProcessInstruction() local
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H A D | HexagonOptAddrMode.cpp | 86 const HexagonRegisterInfo *HRI = nullptr; global() member in __anonf245222f0111::HexagonOptAddrMode
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H A D | HexagonVLIWPacketizer.cpp | 117 const HexagonRegisterInfo *HRI = nullptr; member in __anon54e4cf100111::HexagonPacketizer [all...] |
H A D | HexagonGenInsert.cpp | 568 const HexagonRegisterInfo *HRI = nullptr; member in __anon494378ab0511::HexagonGenInsert [all...] |
H A D | HexagonISelDAGToDAG.cpp | 1428 auto &HRI = *HST.getRegisterInfo(); in emitFunctionEntryCode() local
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H A D | HexagonConstPropagation.cpp | 1887 const HexagonRegisterInfo &HRI; member in __anonbef353470611::HexagonConstEvaluator
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