1 /* $NetBSD: hix5hd2-clock.h,v 1.1.1.2 2020/01/03 14:33:04 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (c) 2014 Linaro Ltd. 6 * Copyright (c) 2014 Hisilicon Limited. 7 */ 8 9 #ifndef __DTS_HIX5HD2_CLOCK_H 10 #define __DTS_HIX5HD2_CLOCK_H 11 12 /* fixed rate */ 13 #define HIX5HD2_FIXED_1200M 1 14 #define HIX5HD2_FIXED_400M 2 15 #define HIX5HD2_FIXED_48M 3 16 #define HIX5HD2_FIXED_24M 4 17 #define HIX5HD2_FIXED_600M 5 18 #define HIX5HD2_FIXED_300M 6 19 #define HIX5HD2_FIXED_75M 7 20 #define HIX5HD2_FIXED_200M 8 21 #define HIX5HD2_FIXED_100M 9 22 #define HIX5HD2_FIXED_40M 10 23 #define HIX5HD2_FIXED_150M 11 24 #define HIX5HD2_FIXED_1728M 12 25 #define HIX5HD2_FIXED_28P8M 13 26 #define HIX5HD2_FIXED_432M 14 27 #define HIX5HD2_FIXED_345P6M 15 28 #define HIX5HD2_FIXED_288M 16 29 #define HIX5HD2_FIXED_60M 17 30 #define HIX5HD2_FIXED_750M 18 31 #define HIX5HD2_FIXED_500M 19 32 #define HIX5HD2_FIXED_54M 20 33 #define HIX5HD2_FIXED_27M 21 34 #define HIX5HD2_FIXED_1500M 22 35 #define HIX5HD2_FIXED_375M 23 36 #define HIX5HD2_FIXED_187M 24 37 #define HIX5HD2_FIXED_250M 25 38 #define HIX5HD2_FIXED_125M 26 39 #define HIX5HD2_FIXED_2P02M 27 40 #define HIX5HD2_FIXED_50M 28 41 #define HIX5HD2_FIXED_25M 29 42 #define HIX5HD2_FIXED_83M 30 43 44 /* mux clocks */ 45 #define HIX5HD2_SFC_MUX 64 46 #define HIX5HD2_MMC_MUX 65 47 #define HIX5HD2_FEPHY_MUX 66 48 #define HIX5HD2_SD_MUX 67 49 50 /* gate clocks */ 51 #define HIX5HD2_SFC_RST 128 52 #define HIX5HD2_SFC_CLK 129 53 #define HIX5HD2_MMC_CIU_CLK 130 54 #define HIX5HD2_MMC_BIU_CLK 131 55 #define HIX5HD2_MMC_CIU_RST 132 56 #define HIX5HD2_FWD_BUS_CLK 133 57 #define HIX5HD2_FWD_SYS_CLK 134 58 #define HIX5HD2_MAC0_PHY_CLK 135 59 #define HIX5HD2_SD_CIU_CLK 136 60 #define HIX5HD2_SD_BIU_CLK 137 61 #define HIX5HD2_SD_CIU_RST 138 62 #define HIX5HD2_WDG0_CLK 139 63 #define HIX5HD2_WDG0_RST 140 64 #define HIX5HD2_I2C0_CLK 141 65 #define HIX5HD2_I2C0_RST 142 66 #define HIX5HD2_I2C1_CLK 143 67 #define HIX5HD2_I2C1_RST 144 68 #define HIX5HD2_I2C2_CLK 145 69 #define HIX5HD2_I2C2_RST 146 70 #define HIX5HD2_I2C3_CLK 147 71 #define HIX5HD2_I2C3_RST 148 72 #define HIX5HD2_I2C4_CLK 149 73 #define HIX5HD2_I2C4_RST 150 74 #define HIX5HD2_I2C5_CLK 151 75 #define HIX5HD2_I2C5_RST 152 76 77 /* complex */ 78 #define HIX5HD2_MAC0_CLK 192 79 #define HIX5HD2_MAC1_CLK 193 80 #define HIX5HD2_SATA_CLK 194 81 #define HIX5HD2_USB_CLK 195 82 83 #define HIX5HD2_NR_CLKS 256 84 #endif /* __DTS_HIX5HD2_CLOCK_H */ 85