1 //===-- RegisterInfoPOSIX_arm64.cpp ---------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===---------------------------------------------------------------------===// 8 9 #include <cassert> 10 #include <cstddef> 11 #include <vector> 12 13 #include "lldb/lldb-defines.h" 14 #include "llvm/Support/Compiler.h" 15 16 #include "RegisterInfoPOSIX_arm64.h" 17 18 // Based on RegisterContextDarwin_arm64.cpp 19 #define GPR_OFFSET(idx) ((idx)*8) 20 #define GPR_OFFSET_NAME(reg) \ 21 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::GPR, reg)) 22 23 #define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterInfoPOSIX_arm64::GPR)) 24 #define FPU_OFFSET_NAME(reg) \ 25 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::FPU, reg) + \ 26 sizeof(RegisterInfoPOSIX_arm64::GPR)) 27 28 // This information is based on AArch64 with SVE architecture reference manual. 29 // AArch64 with SVE has 32 Z and 16 P vector registers. There is also an FFR 30 // (First Fault) register and a VG (Vector Granule) pseudo register. 31 32 // SVE 16-byte quad word is the basic unit of expansion in vector length. 33 #define SVE_QUAD_WORD_BYTES 16 34 35 // Vector length is the multiplier which decides the no of quad words, 36 // (multiples of 128-bits or 16-bytes) present in a Z register. Vector length 37 // is decided during execution and can change at runtime. SVE AArch64 register 38 // infos have modes one for each valid value of vector length. A change in 39 // vector length requires register context to update sizes of SVE Z, P and FFR. 40 // Also register context needs to update byte offsets of all registers affected 41 // by the change in vector length. 42 #define SVE_REGS_DEFAULT_OFFSET_LINUX sizeof(RegisterInfoPOSIX_arm64::GPR) 43 44 #define SVE_OFFSET_VG SVE_REGS_DEFAULT_OFFSET_LINUX 45 46 #define EXC_OFFSET_NAME(reg) \ 47 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::EXC, reg) + \ 48 sizeof(RegisterInfoPOSIX_arm64::GPR) + \ 49 sizeof(RegisterInfoPOSIX_arm64::FPU)) 50 #define DBG_OFFSET_NAME(reg) \ 51 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::DBG, reg) + \ 52 sizeof(RegisterInfoPOSIX_arm64::GPR) + \ 53 sizeof(RegisterInfoPOSIX_arm64::FPU) + \ 54 sizeof(RegisterInfoPOSIX_arm64::EXC)) 55 56 #define DEFINE_DBG(reg, i) \ 57 #reg, NULL, \ 58 sizeof(((RegisterInfoPOSIX_arm64::DBG *) NULL)->reg[i]), \ 59 DBG_OFFSET_NAME(reg[i]), lldb::eEncodingUint, lldb::eFormatHex, \ 60 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 61 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 62 dbg_##reg##i }, \ 63 NULL, NULL, NULL, 64 #define REG_CONTEXT_SIZE \ 65 (sizeof(RegisterInfoPOSIX_arm64::GPR) + \ 66 sizeof(RegisterInfoPOSIX_arm64::FPU) + \ 67 sizeof(RegisterInfoPOSIX_arm64::EXC)) 68 69 // Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure. 70 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT 71 #include "RegisterInfos_arm64.h" 72 #include "RegisterInfos_arm64_sve.h" 73 #undef DECLARE_REGISTER_INFOS_ARM64_STRUCT 74 75 static lldb_private::RegisterInfo g_register_infos_pauth[] = { 76 DEFINE_EXTENSION_REG(data_mask), DEFINE_EXTENSION_REG(code_mask)}; 77 78 static lldb_private::RegisterInfo g_register_infos_mte[] = { 79 DEFINE_EXTENSION_REG(mte_ctrl)}; 80 81 static lldb_private::RegisterInfo g_register_infos_tls[] = { 82 DEFINE_EXTENSION_REG(tpidr), 83 // Only present when SME is present 84 DEFINE_EXTENSION_REG(tpidr2)}; 85 86 static lldb_private::RegisterInfo g_register_infos_sme[] = { 87 DEFINE_EXTENSION_REG(svcr), 88 DEFINE_EXTENSION_REG(svg), 89 // 16 is a default size we will change later. 90 {"za", nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, 91 KIND_ALL_INVALID, nullptr, nullptr, nullptr}}; 92 93 static lldb_private::RegisterInfo g_register_infos_sme2[] = { 94 {"zt0", nullptr, 64, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, 95 KIND_ALL_INVALID, nullptr, nullptr, nullptr}}; 96 97 static lldb_private::RegisterInfo g_register_infos_fpmr[] = { 98 DEFINE_EXTENSION_REG(fpmr)}; 99 100 static lldb_private::RegisterInfo g_register_infos_gcs[] = { 101 DEFINE_EXTENSION_REG(gcs_features_enabled), 102 DEFINE_EXTENSION_REG(gcs_features_locked), DEFINE_EXTENSION_REG(gcspr_el0)}; 103 104 // Number of register sets provided by this context. 105 enum { 106 k_num_gpr_registers = gpr_w28 - gpr_x0 + 1, 107 k_num_fpr_registers = fpu_fpcr - fpu_v0 + 1, 108 k_num_sve_registers = sve_ffr - sve_vg + 1, 109 k_num_mte_register = 1, 110 // Number of TLS registers is dynamic so it is not listed here. 111 k_num_pauth_register = 2, 112 // SME2's ZT0 will also be added to this set if present. So this number is 113 // only for SME1 registers. 114 k_num_sme_register = 3, 115 k_num_fpmr_register = 1, 116 k_num_gcs_register = 3, 117 k_num_register_sets_default = 2, 118 k_num_register_sets = 3 119 }; 120 121 // ARM64 general purpose registers. 122 static const uint32_t g_gpr_regnums_arm64[] = { 123 gpr_x0, gpr_x1, gpr_x2, gpr_x3, 124 gpr_x4, gpr_x5, gpr_x6, gpr_x7, 125 gpr_x8, gpr_x9, gpr_x10, gpr_x11, 126 gpr_x12, gpr_x13, gpr_x14, gpr_x15, 127 gpr_x16, gpr_x17, gpr_x18, gpr_x19, 128 gpr_x20, gpr_x21, gpr_x22, gpr_x23, 129 gpr_x24, gpr_x25, gpr_x26, gpr_x27, 130 gpr_x28, gpr_fp, gpr_lr, gpr_sp, 131 gpr_pc, gpr_cpsr, gpr_w0, gpr_w1, 132 gpr_w2, gpr_w3, gpr_w4, gpr_w5, 133 gpr_w6, gpr_w7, gpr_w8, gpr_w9, 134 gpr_w10, gpr_w11, gpr_w12, gpr_w13, 135 gpr_w14, gpr_w15, gpr_w16, gpr_w17, 136 gpr_w18, gpr_w19, gpr_w20, gpr_w21, 137 gpr_w22, gpr_w23, gpr_w24, gpr_w25, 138 gpr_w26, gpr_w27, gpr_w28, LLDB_INVALID_REGNUM}; 139 140 static_assert(((sizeof g_gpr_regnums_arm64 / sizeof g_gpr_regnums_arm64[0]) - 141 1) == k_num_gpr_registers, 142 "g_gpr_regnums_arm64 has wrong number of register infos"); 143 144 // ARM64 floating point registers. 145 static const uint32_t g_fpu_regnums_arm64[] = { 146 fpu_v0, fpu_v1, fpu_v2, 147 fpu_v3, fpu_v4, fpu_v5, 148 fpu_v6, fpu_v7, fpu_v8, 149 fpu_v9, fpu_v10, fpu_v11, 150 fpu_v12, fpu_v13, fpu_v14, 151 fpu_v15, fpu_v16, fpu_v17, 152 fpu_v18, fpu_v19, fpu_v20, 153 fpu_v21, fpu_v22, fpu_v23, 154 fpu_v24, fpu_v25, fpu_v26, 155 fpu_v27, fpu_v28, fpu_v29, 156 fpu_v30, fpu_v31, fpu_s0, 157 fpu_s1, fpu_s2, fpu_s3, 158 fpu_s4, fpu_s5, fpu_s6, 159 fpu_s7, fpu_s8, fpu_s9, 160 fpu_s10, fpu_s11, fpu_s12, 161 fpu_s13, fpu_s14, fpu_s15, 162 fpu_s16, fpu_s17, fpu_s18, 163 fpu_s19, fpu_s20, fpu_s21, 164 fpu_s22, fpu_s23, fpu_s24, 165 fpu_s25, fpu_s26, fpu_s27, 166 fpu_s28, fpu_s29, fpu_s30, 167 fpu_s31, fpu_d0, fpu_d1, 168 fpu_d2, fpu_d3, fpu_d4, 169 fpu_d5, fpu_d6, fpu_d7, 170 fpu_d8, fpu_d9, fpu_d10, 171 fpu_d11, fpu_d12, fpu_d13, 172 fpu_d14, fpu_d15, fpu_d16, 173 fpu_d17, fpu_d18, fpu_d19, 174 fpu_d20, fpu_d21, fpu_d22, 175 fpu_d23, fpu_d24, fpu_d25, 176 fpu_d26, fpu_d27, fpu_d28, 177 fpu_d29, fpu_d30, fpu_d31, 178 fpu_fpsr, fpu_fpcr, LLDB_INVALID_REGNUM}; 179 static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) - 180 1) == k_num_fpr_registers, 181 "g_fpu_regnums_arm64 has wrong number of register infos"); 182 183 // ARM64 SVE registers. 184 static const uint32_t g_sve_regnums_arm64[] = { 185 sve_vg, sve_z0, sve_z1, 186 sve_z2, sve_z3, sve_z4, 187 sve_z5, sve_z6, sve_z7, 188 sve_z8, sve_z9, sve_z10, 189 sve_z11, sve_z12, sve_z13, 190 sve_z14, sve_z15, sve_z16, 191 sve_z17, sve_z18, sve_z19, 192 sve_z20, sve_z21, sve_z22, 193 sve_z23, sve_z24, sve_z25, 194 sve_z26, sve_z27, sve_z28, 195 sve_z29, sve_z30, sve_z31, 196 sve_p0, sve_p1, sve_p2, 197 sve_p3, sve_p4, sve_p5, 198 sve_p6, sve_p7, sve_p8, 199 sve_p9, sve_p10, sve_p11, 200 sve_p12, sve_p13, sve_p14, 201 sve_p15, sve_ffr, LLDB_INVALID_REGNUM}; 202 static_assert(((sizeof g_sve_regnums_arm64 / sizeof g_sve_regnums_arm64[0]) - 203 1) == k_num_sve_registers, 204 "g_sve_regnums_arm64 has wrong number of register infos"); 205 206 // Register sets for ARM64. 207 static const lldb_private::RegisterSet g_reg_sets_arm64[k_num_register_sets] = { 208 {"General Purpose Registers", "gpr", k_num_gpr_registers, 209 g_gpr_regnums_arm64}, 210 {"Floating Point Registers", "fpu", k_num_fpr_registers, 211 g_fpu_regnums_arm64}, 212 {"Scalable Vector Extension Registers", "sve", k_num_sve_registers, 213 g_sve_regnums_arm64}}; 214 215 static const lldb_private::RegisterSet g_reg_set_pauth_arm64 = { 216 "Pointer Authentication Registers", "pauth", k_num_pauth_register, nullptr}; 217 218 static const lldb_private::RegisterSet g_reg_set_mte_arm64 = { 219 "MTE Control Register", "mte", k_num_mte_register, nullptr}; 220 221 // The size of the TLS set is dynamic, so not listed here. 222 223 static const lldb_private::RegisterSet g_reg_set_sme_arm64 = { 224 "Scalable Matrix Extension Registers", "sme", k_num_sme_register, nullptr}; 225 226 static const lldb_private::RegisterSet g_reg_set_fpmr_arm64 = { 227 "Floating Point Mode Register", "fpmr", k_num_fpmr_register, nullptr}; 228 229 static const lldb_private::RegisterSet g_reg_set_gcs_arm64 = { 230 "Guarded Control Stack Registers", "gcs", k_num_gcs_register, nullptr}; 231 232 RegisterInfoPOSIX_arm64::RegisterInfoPOSIX_arm64( 233 const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets) 234 : lldb_private::RegisterInfoAndSetInterface(target_arch), 235 m_opt_regsets(opt_regsets) { 236 switch (target_arch.GetMachine()) { 237 case llvm::Triple::aarch64: 238 case llvm::Triple::aarch64_32: { 239 m_register_set_p = g_reg_sets_arm64; 240 m_register_set_count = k_num_register_sets_default; 241 m_per_regset_regnum_range[GPRegSet] = std::make_pair(gpr_x0, gpr_w28 + 1); 242 m_per_regset_regnum_range[FPRegSet] = std::make_pair(fpu_v0, fpu_fpcr + 1); 243 244 // Now configure register sets supported by current target. If we have a 245 // dynamic register set like MTE, Pointer Authentication regset then we need 246 // to create dynamic register infos and regset array. Push back all optional 247 // register infos and regset and calculate register offsets accordingly. 248 if (m_opt_regsets.AnySet(eRegsetMaskSVE | eRegsetMaskSSVE)) { 249 m_register_info_p = g_register_infos_arm64_sve_le; 250 m_register_info_count = sve_ffr + 1; 251 m_per_regset_regnum_range[m_register_set_count++] = 252 std::make_pair(sve_vg, sve_ffr + 1); 253 } else { 254 m_register_info_p = g_register_infos_arm64_le; 255 m_register_info_count = fpu_fpcr + 1; 256 } 257 258 if (m_opt_regsets.AnySet(eRegsetMaskDynamic)) { 259 llvm::ArrayRef<lldb_private::RegisterInfo> reg_infos_ref = 260 llvm::ArrayRef(m_register_info_p, m_register_info_count); 261 llvm::ArrayRef<lldb_private::RegisterSet> reg_sets_ref = 262 llvm::ArrayRef(m_register_set_p, m_register_set_count); 263 llvm::copy(reg_infos_ref, std::back_inserter(m_dynamic_reg_infos)); 264 llvm::copy(reg_sets_ref, std::back_inserter(m_dynamic_reg_sets)); 265 266 if (m_opt_regsets.AllSet(eRegsetMaskPAuth)) 267 AddRegSetPAuth(); 268 269 if (m_opt_regsets.AllSet(eRegsetMaskMTE)) 270 AddRegSetMTE(); 271 272 if (m_opt_regsets.AllSet(eRegsetMaskTLS)) { 273 // The TLS set always contains tpidr but only has tpidr2 when SME is 274 // present. 275 AddRegSetTLS(m_opt_regsets.AllSet(eRegsetMaskSSVE)); 276 } 277 278 if (m_opt_regsets.AnySet(eRegsetMaskSSVE)) 279 AddRegSetSME(m_opt_regsets.AnySet(eRegsetMaskZT)); 280 281 if (m_opt_regsets.AllSet(eRegsetMaskFPMR)) 282 AddRegSetFPMR(); 283 284 if (m_opt_regsets.AllSet(eRegsetMaskGCS)) 285 AddRegSetGCS(); 286 287 m_register_info_count = m_dynamic_reg_infos.size(); 288 m_register_info_p = m_dynamic_reg_infos.data(); 289 m_register_set_p = m_dynamic_reg_sets.data(); 290 m_register_set_count = m_dynamic_reg_sets.size(); 291 } 292 break; 293 } 294 default: 295 assert(false && "Unhandled target architecture."); 296 } 297 } 298 299 uint32_t RegisterInfoPOSIX_arm64::GetRegisterCount() const { 300 return m_register_info_count; 301 } 302 303 size_t RegisterInfoPOSIX_arm64::GetGPRSizeStatic() { 304 return sizeof(struct RegisterInfoPOSIX_arm64::GPR); 305 } 306 307 size_t RegisterInfoPOSIX_arm64::GetFPRSize() const { 308 return sizeof(struct RegisterInfoPOSIX_arm64::FPU); 309 } 310 311 const lldb_private::RegisterInfo * 312 RegisterInfoPOSIX_arm64::GetRegisterInfo() const { 313 return m_register_info_p; 314 } 315 316 size_t RegisterInfoPOSIX_arm64::GetRegisterSetCount() const { 317 return m_register_set_count; 318 } 319 320 size_t RegisterInfoPOSIX_arm64::GetRegisterSetFromRegisterIndex( 321 uint32_t reg_index) const { 322 for (const auto ®set_range : m_per_regset_regnum_range) { 323 if (reg_index >= regset_range.second.first && 324 reg_index < regset_range.second.second) 325 return regset_range.first; 326 } 327 return LLDB_INVALID_REGNUM; 328 } 329 330 const lldb_private::RegisterSet * 331 RegisterInfoPOSIX_arm64::GetRegisterSet(size_t set_index) const { 332 if (set_index < GetRegisterSetCount()) 333 return &m_register_set_p[set_index]; 334 return nullptr; 335 } 336 337 void RegisterInfoPOSIX_arm64::AddRegSetPAuth() { 338 uint32_t pa_regnum = m_dynamic_reg_infos.size(); 339 for (uint32_t i = 0; i < k_num_pauth_register; i++) { 340 pauth_regnum_collection.push_back(pa_regnum + i); 341 m_dynamic_reg_infos.push_back(g_register_infos_pauth[i]); 342 m_dynamic_reg_infos[pa_regnum + i].byte_offset = 343 m_dynamic_reg_infos[pa_regnum + i - 1].byte_offset + 344 m_dynamic_reg_infos[pa_regnum + i - 1].byte_size; 345 m_dynamic_reg_infos[pa_regnum + i].kinds[lldb::eRegisterKindLLDB] = 346 pa_regnum + i; 347 } 348 349 m_per_regset_regnum_range[m_register_set_count] = 350 std::make_pair(pa_regnum, m_dynamic_reg_infos.size()); 351 m_dynamic_reg_sets.push_back(g_reg_set_pauth_arm64); 352 m_dynamic_reg_sets.back().registers = pauth_regnum_collection.data(); 353 } 354 355 void RegisterInfoPOSIX_arm64::AddRegSetMTE() { 356 uint32_t mte_regnum = m_dynamic_reg_infos.size(); 357 m_mte_regnum_collection.push_back(mte_regnum); 358 m_dynamic_reg_infos.push_back(g_register_infos_mte[0]); 359 m_dynamic_reg_infos[mte_regnum].byte_offset = 360 m_dynamic_reg_infos[mte_regnum - 1].byte_offset + 361 m_dynamic_reg_infos[mte_regnum - 1].byte_size; 362 m_dynamic_reg_infos[mte_regnum].kinds[lldb::eRegisterKindLLDB] = mte_regnum; 363 364 m_per_regset_regnum_range[m_register_set_count] = 365 std::make_pair(mte_regnum, mte_regnum + 1); 366 m_dynamic_reg_sets.push_back(g_reg_set_mte_arm64); 367 m_dynamic_reg_sets.back().registers = m_mte_regnum_collection.data(); 368 } 369 370 void RegisterInfoPOSIX_arm64::AddRegSetTLS(bool has_tpidr2) { 371 uint32_t tls_regnum = m_dynamic_reg_infos.size(); 372 uint32_t num_regs = has_tpidr2 ? 2 : 1; 373 for (uint32_t i = 0; i < num_regs; i++) { 374 m_tls_regnum_collection.push_back(tls_regnum + i); 375 m_dynamic_reg_infos.push_back(g_register_infos_tls[i]); 376 m_dynamic_reg_infos[tls_regnum + i].byte_offset = 377 m_dynamic_reg_infos[tls_regnum + i - 1].byte_offset + 378 m_dynamic_reg_infos[tls_regnum + i - 1].byte_size; 379 m_dynamic_reg_infos[tls_regnum + i].kinds[lldb::eRegisterKindLLDB] = 380 tls_regnum + i; 381 } 382 383 m_per_regset_regnum_range[m_register_set_count] = 384 std::make_pair(tls_regnum, m_dynamic_reg_infos.size()); 385 m_dynamic_reg_sets.push_back( 386 {"Thread Local Storage Registers", "tls", num_regs, nullptr}); 387 m_dynamic_reg_sets.back().registers = m_tls_regnum_collection.data(); 388 } 389 390 void RegisterInfoPOSIX_arm64::AddRegSetSME(bool has_zt) { 391 const uint32_t first_sme_regnum = m_dynamic_reg_infos.size(); 392 uint32_t sme_regnum = first_sme_regnum; 393 394 for (uint32_t i = 0; i < k_num_sme_register; ++i, ++sme_regnum) { 395 m_sme_regnum_collection.push_back(sme_regnum); 396 m_dynamic_reg_infos.push_back(g_register_infos_sme[i]); 397 m_dynamic_reg_infos[sme_regnum].byte_offset = 398 m_dynamic_reg_infos[sme_regnum - 1].byte_offset + 399 m_dynamic_reg_infos[sme_regnum - 1].byte_size; 400 m_dynamic_reg_infos[sme_regnum].kinds[lldb::eRegisterKindLLDB] = sme_regnum; 401 } 402 403 lldb_private::RegisterSet sme_regset = g_reg_set_sme_arm64; 404 405 if (has_zt) { 406 m_sme_regnum_collection.push_back(sme_regnum); 407 m_dynamic_reg_infos.push_back(g_register_infos_sme2[0]); 408 m_dynamic_reg_infos[sme_regnum].byte_offset = 409 m_dynamic_reg_infos[sme_regnum - 1].byte_offset + 410 m_dynamic_reg_infos[sme_regnum - 1].byte_size; 411 m_dynamic_reg_infos[sme_regnum].kinds[lldb::eRegisterKindLLDB] = sme_regnum; 412 413 sme_regset.num_registers += 1; 414 } 415 416 m_per_regset_regnum_range[m_register_set_count] = 417 std::make_pair(first_sme_regnum, m_dynamic_reg_infos.size()); 418 m_dynamic_reg_sets.push_back(sme_regset); 419 m_dynamic_reg_sets.back().registers = m_sme_regnum_collection.data(); 420 421 // When vg is written during streaming mode, svg will also change, as vg and 422 // svg in this state are both showing the streaming vector length. 423 // We model this as vg invalidating svg. In non-streaming mode this doesn't 424 // happen but to keep things simple we will invalidate svg anyway. 425 // 426 // This must be added now, rather than when vg is defined because SME is a 427 // dynamic set that may or may not be present. 428 static uint32_t vg_invalidates[] = {sme_regnum + 1 /*svg*/, 429 LLDB_INVALID_REGNUM}; 430 m_dynamic_reg_infos[GetRegNumSVEVG()].invalidate_regs = vg_invalidates; 431 } 432 433 void RegisterInfoPOSIX_arm64::AddRegSetFPMR() { 434 uint32_t fpmr_regnum = m_dynamic_reg_infos.size(); 435 m_fpmr_regnum_collection.push_back(fpmr_regnum); 436 m_dynamic_reg_infos.push_back(g_register_infos_fpmr[0]); 437 m_dynamic_reg_infos[fpmr_regnum].byte_offset = 438 m_dynamic_reg_infos[fpmr_regnum - 1].byte_offset + 439 m_dynamic_reg_infos[fpmr_regnum - 1].byte_size; 440 m_dynamic_reg_infos[fpmr_regnum].kinds[lldb::eRegisterKindLLDB] = fpmr_regnum; 441 442 m_per_regset_regnum_range[m_register_set_count] = 443 std::make_pair(fpmr_regnum, fpmr_regnum + 1); 444 m_dynamic_reg_sets.push_back(g_reg_set_fpmr_arm64); 445 m_dynamic_reg_sets.back().registers = m_fpmr_regnum_collection.data(); 446 } 447 448 void RegisterInfoPOSIX_arm64::AddRegSetGCS() { 449 uint32_t gcs_regnum = m_dynamic_reg_infos.size(); 450 for (uint32_t i = 0; i < k_num_gcs_register; i++) { 451 m_gcs_regnum_collection.push_back(gcs_regnum + i); 452 m_dynamic_reg_infos.push_back(g_register_infos_gcs[i]); 453 m_dynamic_reg_infos[gcs_regnum + i].byte_offset = 454 m_dynamic_reg_infos[gcs_regnum + i - 1].byte_offset + 455 m_dynamic_reg_infos[gcs_regnum + i - 1].byte_size; 456 m_dynamic_reg_infos[gcs_regnum + i].kinds[lldb::eRegisterKindLLDB] = 457 gcs_regnum + i; 458 } 459 460 m_per_regset_regnum_range[m_register_set_count] = 461 std::make_pair(gcs_regnum, m_dynamic_reg_infos.size()); 462 m_dynamic_reg_sets.push_back(g_reg_set_gcs_arm64); 463 m_dynamic_reg_sets.back().registers = m_gcs_regnum_collection.data(); 464 } 465 466 uint32_t RegisterInfoPOSIX_arm64::ConfigureVectorLengthSVE(uint32_t sve_vq) { 467 // sve_vq contains SVE Quad vector length in context of AArch64 SVE. 468 // SVE register infos if enabled cannot be disabled by selecting sve_vq = 0. 469 // Also if an invalid or previously set vector length is passed to this 470 // function then it will exit immediately with previously set vector length. 471 if (!VectorSizeIsValid(sve_vq) || m_vector_reg_vq == sve_vq) 472 return m_vector_reg_vq; 473 474 // We cannot enable AArch64 only mode if SVE was enabled. 475 if (sve_vq == eVectorQuadwordAArch64 && 476 m_vector_reg_vq > eVectorQuadwordAArch64) 477 sve_vq = eVectorQuadwordAArch64SVE; 478 479 m_vector_reg_vq = sve_vq; 480 481 if (sve_vq == eVectorQuadwordAArch64) 482 return m_vector_reg_vq; 483 std::vector<lldb_private::RegisterInfo> ®_info_ref = 484 m_per_vq_reg_infos[sve_vq]; 485 486 if (reg_info_ref.empty()) { 487 reg_info_ref = llvm::ArrayRef(m_register_info_p, m_register_info_count); 488 489 uint32_t offset = SVE_REGS_DEFAULT_OFFSET_LINUX; 490 reg_info_ref[fpu_fpsr].byte_offset = offset; 491 reg_info_ref[fpu_fpcr].byte_offset = offset + 4; 492 reg_info_ref[sve_vg].byte_offset = offset + 8; 493 offset += 16; 494 495 // Update Z registers size and offset 496 uint32_t s_reg_base = fpu_s0; 497 uint32_t d_reg_base = fpu_d0; 498 uint32_t v_reg_base = fpu_v0; 499 uint32_t z_reg_base = sve_z0; 500 501 for (uint32_t index = 0; index < 32; index++) { 502 reg_info_ref[s_reg_base + index].byte_offset = offset; 503 reg_info_ref[d_reg_base + index].byte_offset = offset; 504 reg_info_ref[v_reg_base + index].byte_offset = offset; 505 reg_info_ref[z_reg_base + index].byte_offset = offset; 506 507 reg_info_ref[z_reg_base + index].byte_size = sve_vq * SVE_QUAD_WORD_BYTES; 508 offset += reg_info_ref[z_reg_base + index].byte_size; 509 } 510 511 // Update P registers and FFR size and offset 512 for (uint32_t it = sve_p0; it <= sve_ffr; it++) { 513 reg_info_ref[it].byte_offset = offset; 514 reg_info_ref[it].byte_size = sve_vq * SVE_QUAD_WORD_BYTES / 8; 515 offset += reg_info_ref[it].byte_size; 516 } 517 518 for (uint32_t it = sve_ffr + 1; it < m_register_info_count; it++) { 519 reg_info_ref[it].byte_offset = offset; 520 offset += reg_info_ref[it].byte_size; 521 } 522 523 m_per_vq_reg_infos[sve_vq] = reg_info_ref; 524 } 525 526 m_register_info_p = m_per_vq_reg_infos[sve_vq].data(); 527 return m_vector_reg_vq; 528 } 529 530 void RegisterInfoPOSIX_arm64::ConfigureVectorLengthZA(uint32_t za_vq) { 531 if (!VectorSizeIsValid(za_vq) || m_za_reg_vq == za_vq) 532 return; 533 534 m_za_reg_vq = za_vq; 535 536 // For SVE changes, we replace m_register_info_p completely. ZA is in a 537 // dynamic set and is just 1 register so we make an exception to const here. 538 lldb_private::RegisterInfo *non_const_reginfo = 539 const_cast<lldb_private::RegisterInfo *>(m_register_info_p); 540 non_const_reginfo[m_sme_regnum_collection[2]].byte_size = 541 (za_vq * 16) * (za_vq * 16); 542 } 543 544 bool RegisterInfoPOSIX_arm64::IsSVEReg(unsigned reg) const { 545 if (m_vector_reg_vq > eVectorQuadwordAArch64) 546 return (sve_vg <= reg && reg <= sve_ffr); 547 else 548 return false; 549 } 550 551 bool RegisterInfoPOSIX_arm64::IsSVEZReg(unsigned reg) const { 552 return (sve_z0 <= reg && reg <= sve_z31); 553 } 554 555 bool RegisterInfoPOSIX_arm64::IsSVEPReg(unsigned reg) const { 556 return (sve_p0 <= reg && reg <= sve_p15); 557 } 558 559 bool RegisterInfoPOSIX_arm64::IsSVERegVG(unsigned reg) const { 560 return sve_vg == reg; 561 } 562 563 bool RegisterInfoPOSIX_arm64::IsSMERegZA(unsigned reg) const { 564 return reg == m_sme_regnum_collection[2]; 565 } 566 567 bool RegisterInfoPOSIX_arm64::IsSMERegZT(unsigned reg) const { 568 // ZT0 is part of the SME register set only if SME2 is present. 569 return m_sme_regnum_collection.size() >= 4 && 570 reg == m_sme_regnum_collection[3]; 571 } 572 573 bool RegisterInfoPOSIX_arm64::IsPAuthReg(unsigned reg) const { 574 return llvm::is_contained(pauth_regnum_collection, reg); 575 } 576 577 bool RegisterInfoPOSIX_arm64::IsMTEReg(unsigned reg) const { 578 return llvm::is_contained(m_mte_regnum_collection, reg); 579 } 580 581 bool RegisterInfoPOSIX_arm64::IsTLSReg(unsigned reg) const { 582 return llvm::is_contained(m_tls_regnum_collection, reg); 583 } 584 585 bool RegisterInfoPOSIX_arm64::IsSMEReg(unsigned reg) const { 586 return llvm::is_contained(m_sme_regnum_collection, reg); 587 } 588 589 bool RegisterInfoPOSIX_arm64::IsFPMRReg(unsigned reg) const { 590 return llvm::is_contained(m_fpmr_regnum_collection, reg); 591 } 592 593 bool RegisterInfoPOSIX_arm64::IsGCSReg(unsigned reg) const { 594 return llvm::is_contained(m_gcs_regnum_collection, reg); 595 } 596 597 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEZ0() const { return sve_z0; } 598 599 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEFFR() const { return sve_ffr; } 600 601 uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPCR() const { return fpu_fpcr; } 602 603 uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPSR() const { return fpu_fpsr; } 604 605 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; } 606 607 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSMESVG() const { 608 return m_sme_regnum_collection[1]; 609 } 610 611 uint32_t RegisterInfoPOSIX_arm64::GetPAuthOffset() const { 612 return m_register_info_p[pauth_regnum_collection[0]].byte_offset; 613 } 614 615 uint32_t RegisterInfoPOSIX_arm64::GetMTEOffset() const { 616 return m_register_info_p[m_mte_regnum_collection[0]].byte_offset; 617 } 618 619 uint32_t RegisterInfoPOSIX_arm64::GetTLSOffset() const { 620 return m_register_info_p[m_tls_regnum_collection[0]].byte_offset; 621 } 622 623 uint32_t RegisterInfoPOSIX_arm64::GetSMEOffset() const { 624 return m_register_info_p[m_sme_regnum_collection[0]].byte_offset; 625 } 626 627 uint32_t RegisterInfoPOSIX_arm64::GetFPMROffset() const { 628 return m_register_info_p[m_fpmr_regnum_collection[0]].byte_offset; 629 } 630 631 uint32_t RegisterInfoPOSIX_arm64::GetGCSOffset() const { 632 return m_register_info_p[m_gcs_regnum_collection[0]].byte_offset; 633 } 634