1 //===-- ArchSpec.cpp ------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "lldb/Utility/ArchSpec.h" 10 #include "lldb/Utility/LLDBLog.h" 11 12 #include "lldb/Utility/Log.h" 13 #include "lldb/Utility/StringList.h" 14 #include "lldb/lldb-defines.h" 15 #include "llvm/ADT/STLExtras.h" 16 #include "llvm/BinaryFormat/COFF.h" 17 #include "llvm/BinaryFormat/ELF.h" 18 #include "llvm/BinaryFormat/MachO.h" 19 #include "llvm/BinaryFormat/XCOFF.h" 20 #include "llvm/Support/Compiler.h" 21 #include "llvm/TargetParser/ARMTargetParser.h" 22 23 using namespace lldb; 24 using namespace lldb_private; 25 26 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 27 bool try_inverse, bool enforce_exact_match); 28 29 namespace lldb_private { 30 31 struct CoreDefinition { 32 ByteOrder default_byte_order; 33 uint32_t addr_byte_size; 34 uint32_t min_opcode_byte_size; 35 uint32_t max_opcode_byte_size; 36 llvm::Triple::ArchType machine; 37 ArchSpec::Core core; 38 const char *const name; 39 }; 40 41 } // namespace lldb_private 42 43 // This core information can be looked using the ArchSpec::Core as the index 44 static const CoreDefinition g_core_definitions[] = { 45 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 46 "arm"}, 47 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 48 "armv4"}, 49 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 50 "armv4t"}, 51 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 52 "armv5"}, 53 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 54 "armv5e"}, 55 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 56 "armv5t"}, 57 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 58 "armv6"}, 59 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 60 "armv6m"}, 61 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 62 "armv7"}, 63 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7a, 64 "armv7a"}, 65 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l, 66 "armv7l"}, 67 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 68 "armv7f"}, 69 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 70 "armv7s"}, 71 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 72 "armv7k"}, 73 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 74 "armv7m"}, 75 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 76 "armv7em"}, 77 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 78 "xscale"}, 79 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 80 "thumb"}, 81 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 82 "thumbv4t"}, 83 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 84 "thumbv5"}, 85 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 86 "thumbv5e"}, 87 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 88 "thumbv6"}, 89 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 90 "thumbv6m"}, 91 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 92 "thumbv7"}, 93 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 94 "thumbv7f"}, 95 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 96 "thumbv7s"}, 97 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 98 "thumbv7k"}, 99 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 100 "thumbv7m"}, 101 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 102 "thumbv7em"}, 103 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 104 ArchSpec::eCore_arm_arm64, "arm64"}, 105 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 106 ArchSpec::eCore_arm_armv8, "armv8"}, 107 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 108 ArchSpec::eCore_arm_armv8a, "armv8a"}, 109 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv8l, 110 "armv8l"}, 111 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 112 ArchSpec::eCore_arm_arm64e, "arm64e"}, 113 {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32, 114 ArchSpec::eCore_arm_arm64_32, "arm64_32"}, 115 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 116 ArchSpec::eCore_arm_aarch64, "aarch64"}, 117 118 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 119 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 120 "mips"}, 121 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 122 "mipsr2"}, 123 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 124 "mipsr3"}, 125 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 126 "mipsr5"}, 127 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 128 "mipsr6"}, 129 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 130 "mipsel"}, 131 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 132 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 133 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 134 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 135 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 136 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 137 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 138 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 139 140 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 141 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 142 "mips64"}, 143 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 144 "mips64r2"}, 145 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 146 "mips64r3"}, 147 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 148 "mips64r5"}, 149 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 150 "mips64r6"}, 151 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 152 ArchSpec::eCore_mips64el, "mips64el"}, 153 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 154 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 155 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 156 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 157 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 158 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 159 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 160 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 161 162 // MSP430 163 {eByteOrderLittle, 2, 2, 4, llvm::Triple::msp430, ArchSpec::eCore_msp430, 164 "msp430"}, 165 166 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 167 "powerpc"}, 168 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 169 "ppc601"}, 170 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 171 "ppc602"}, 172 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 173 "ppc603"}, 174 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 175 "ppc603e"}, 176 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 177 "ppc603ev"}, 178 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 179 "ppc604"}, 180 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 181 "ppc604e"}, 182 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 183 "ppc620"}, 184 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 185 "ppc750"}, 186 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 187 "ppc7400"}, 188 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 189 "ppc7450"}, 190 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 191 "ppc970"}, 192 193 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 194 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 195 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 196 "powerpc64"}, 197 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 198 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 199 200 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 201 ArchSpec::eCore_s390x_generic, "s390x"}, 202 203 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 204 ArchSpec::eCore_sparc_generic, "sparc"}, 205 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 206 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 207 208 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 209 "i386"}, 210 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 211 "i486"}, 212 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 213 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 214 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 215 "i686"}, 216 217 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 218 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 219 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 220 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 221 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 222 ArchSpec::eCore_x86_64_amd64, "amd64"}, 223 224 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 225 ArchSpec::eCore_hexagon_generic, "hexagon"}, 226 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 227 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 228 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 229 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 230 231 {eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32, ArchSpec::eCore_riscv32, 232 "riscv32"}, 233 {eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64, ArchSpec::eCore_riscv64, 234 "riscv64"}, 235 236 {eByteOrderLittle, 4, 4, 4, llvm::Triple::loongarch32, 237 ArchSpec::eCore_loongarch32, "loongarch32"}, 238 {eByteOrderLittle, 8, 4, 4, llvm::Triple::loongarch64, 239 ArchSpec::eCore_loongarch64, "loongarch64"}, 240 241 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 242 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 243 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 244 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 245 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"}, 246 247 {eByteOrderLittle, 2, 2, 4, llvm::Triple::avr, ArchSpec::eCore_avr, "avr"}, 248 249 {eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32, 250 "wasm32"}, 251 }; 252 253 // Ensure that we have an entry in the g_core_definitions for each core. If you 254 // comment out an entry above, you will need to comment out the corresponding 255 // ArchSpec::Core enumeration. 256 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 257 ArchSpec::kNumCores, 258 "make sure we have one core definition for each core"); 259 260 struct ArchDefinitionEntry { 261 ArchSpec::Core core; 262 uint32_t cpu; 263 uint32_t sub; 264 uint32_t cpu_mask; 265 uint32_t sub_mask; 266 }; 267 268 struct ArchDefinition { 269 ArchitectureType type; 270 size_t num_entries; 271 const ArchDefinitionEntry *entries; 272 const char *name; 273 }; 274 275 void ArchSpec::ListSupportedArchNames(StringList &list) { 276 for (const auto &def : g_core_definitions) 277 list.AppendString(def.name); 278 } 279 280 void ArchSpec::AutoComplete(CompletionRequest &request) { 281 for (const auto &def : g_core_definitions) 282 request.TryCompleteCurrentArg(def.name); 283 } 284 285 #define CPU_ANY (UINT32_MAX) 286 287 //===----------------------------------------------------------------------===// 288 // A table that gets searched linearly for matches. This table is used to 289 // convert cpu type and subtypes to architecture names, and to convert 290 // architecture names to cpu types and subtypes. The ordering is important and 291 // allows the precedence to be set when the table is built. 292 #define SUBTYPE_MASK 0x00FFFFFFu 293 294 // clang-format off 295 static const ArchDefinitionEntry g_macho_arch_entries[] = { 296 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, UINT32_MAX, UINT32_MAX}, 297 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK}, 298 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK}, 299 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK}, 300 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK}, 301 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK}, 302 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK}, 303 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK}, 304 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK}, 305 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_XSCALE, UINT32_MAX, SUBTYPE_MASK}, 306 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK}, 307 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK}, 308 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK}, 309 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK}, 310 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK}, 311 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK}, 312 {ArchSpec::eCore_arm_arm64e, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64E, UINT32_MAX, SUBTYPE_MASK}, 313 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_ALL, UINT32_MAX, SUBTYPE_MASK}, 314 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_V8, UINT32_MAX, SUBTYPE_MASK}, 315 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, SUBTYPE_MASK}, 316 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, UINT32_MAX, SUBTYPE_MASK}, 317 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, UINT32_MAX, SUBTYPE_MASK}, 318 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK}, 319 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK}, 320 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK}, 321 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK}, 322 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK}, 323 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK}, 324 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK}, 325 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK}, 326 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK}, 327 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK}, 328 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK}, 329 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK}, 330 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK}, 331 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, UINT32_MAX, UINT32_MAX}, 332 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK}, 333 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_601, UINT32_MAX, SUBTYPE_MASK}, 334 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_602, UINT32_MAX, SUBTYPE_MASK}, 335 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603, UINT32_MAX, SUBTYPE_MASK}, 336 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603e, UINT32_MAX, SUBTYPE_MASK}, 337 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603ev, UINT32_MAX, SUBTYPE_MASK}, 338 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604, UINT32_MAX, SUBTYPE_MASK}, 339 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604e, UINT32_MAX, SUBTYPE_MASK}, 340 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_620, UINT32_MAX, SUBTYPE_MASK}, 341 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_750, UINT32_MAX, SUBTYPE_MASK}, 342 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7400, UINT32_MAX, SUBTYPE_MASK}, 343 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7450, UINT32_MAX, SUBTYPE_MASK}, 344 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_970, UINT32_MAX, SUBTYPE_MASK}, 345 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK}, 346 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK}, 347 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, UINT32_MAX, SUBTYPE_MASK}, 348 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_I386_ALL, UINT32_MAX, SUBTYPE_MASK}, 349 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486, UINT32_MAX, SUBTYPE_MASK}, 350 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486SX, UINT32_MAX, SUBTYPE_MASK}, 351 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, UINT32_MAX, UINT32_MAX}, 352 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_ALL, UINT32_MAX, SUBTYPE_MASK}, 353 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_ARCH1, UINT32_MAX, SUBTYPE_MASK}, 354 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_H, UINT32_MAX, SUBTYPE_MASK}, 355 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, UINT32_MAX, UINT32_MAX}, 356 // Catch any unknown mach architectures so we can always use the object and symbol mach-o files 357 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 358 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 0x00000000u}}; 359 // clang-format on 360 361 static const ArchDefinition g_macho_arch_def = {eArchTypeMachO, 362 std::size(g_macho_arch_entries), 363 g_macho_arch_entries, "mach-o"}; 364 365 //===----------------------------------------------------------------------===// 366 // A table that gets searched linearly for matches. This table is used to 367 // convert cpu type and subtypes to architecture names, and to convert 368 // architecture names to cpu types and subtypes. The ordering is important and 369 // allows the precedence to be set when the table is built. 370 static const ArchDefinitionEntry g_elf_arch_entries[] = { 371 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 372 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 373 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 374 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 375 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 376 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 377 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 378 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 379 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, 380 ArchSpec::eCore_ppc64le_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 381 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, 382 ArchSpec::eCore_ppc64_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 383 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 384 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 385 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 386 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 387 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 388 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 389 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 390 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 391 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 392 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 393 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 394 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 395 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 396 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 397 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 398 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 399 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 400 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 401 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 402 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 403 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 404 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 405 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 406 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 407 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 408 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 409 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 410 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 411 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 412 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 413 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 414 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 415 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 416 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 417 {ArchSpec::eCore_msp430, llvm::ELF::EM_MSP430, LLDB_INVALID_CPUTYPE, 418 0xFFFFFFFFu, 0xFFFFFFFFu}, // MSP430 419 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 420 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 421 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE, 422 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC 423 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 424 0xFFFFFFFFu}, // AVR 425 {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV, 426 ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32 427 {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV, 428 ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64 429 {ArchSpec::eCore_loongarch32, llvm::ELF::EM_LOONGARCH, 430 ArchSpec::eLoongArchSubType_loongarch32, 0xFFFFFFFFu, 431 0xFFFFFFFFu}, // loongarch32 432 {ArchSpec::eCore_loongarch64, llvm::ELF::EM_LOONGARCH, 433 ArchSpec::eLoongArchSubType_loongarch64, 0xFFFFFFFFu, 434 0xFFFFFFFFu}, // loongarch64 435 }; 436 437 static const ArchDefinition g_elf_arch_def = { 438 eArchTypeELF, 439 std::size(g_elf_arch_entries), 440 g_elf_arch_entries, 441 "elf", 442 }; 443 444 static const ArchDefinitionEntry g_coff_arch_entries[] = { 445 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 446 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 447 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 448 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 449 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 450 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 451 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 452 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 453 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 454 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 455 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 456 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 457 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 458 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 459 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64, 460 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64 461 }; 462 463 static const ArchDefinition g_coff_arch_def = { 464 eArchTypeCOFF, 465 std::size(g_coff_arch_entries), 466 g_coff_arch_entries, 467 "pe-coff", 468 }; 469 470 static const ArchDefinitionEntry g_xcoff_arch_entries[] = { 471 {ArchSpec::eCore_ppc_generic, llvm::XCOFF::TCPU_COM, LLDB_INVALID_CPUTYPE, 472 0xFFFFFFFFu, 0xFFFFFFFFu}, 473 {ArchSpec::eCore_ppc64_generic, llvm::XCOFF::TCPU_PPC64, 474 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}}; 475 476 static const ArchDefinition g_xcoff_arch_def = { 477 eArchTypeXCOFF, 478 std::size(g_xcoff_arch_entries), 479 g_xcoff_arch_entries, 480 "xcoff", 481 }; 482 483 //===----------------------------------------------------------------------===// 484 // Table of all ArchDefinitions 485 static const ArchDefinition *g_arch_definitions[] = { 486 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def, &g_xcoff_arch_def}; 487 488 //===----------------------------------------------------------------------===// 489 // Static helper functions. 490 491 // Get the architecture definition for a given object type. 492 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 493 for (const ArchDefinition *def : g_arch_definitions) { 494 if (def->type == arch_type) 495 return def; 496 } 497 return nullptr; 498 } 499 500 // Get an architecture definition by name. 501 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 502 for (const auto &def : g_core_definitions) { 503 if (name.equals_insensitive(def.name)) 504 return &def; 505 } 506 return nullptr; 507 } 508 509 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 510 if (core < std::size(g_core_definitions)) 511 return &g_core_definitions[core]; 512 return nullptr; 513 } 514 515 // Get a definition entry by cpu type and subtype. 516 static const ArchDefinitionEntry * 517 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 518 if (def == nullptr) 519 return nullptr; 520 521 const ArchDefinitionEntry *entries = def->entries; 522 for (size_t i = 0; i < def->num_entries; ++i) { 523 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 524 if (entries[i].sub == (sub & entries[i].sub_mask)) 525 return &entries[i]; 526 } 527 return nullptr; 528 } 529 530 static const ArchDefinitionEntry * 531 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 532 if (def == nullptr) 533 return nullptr; 534 535 const ArchDefinitionEntry *entries = def->entries; 536 for (size_t i = 0; i < def->num_entries; ++i) { 537 if (entries[i].core == core) 538 return &entries[i]; 539 } 540 return nullptr; 541 } 542 543 //===----------------------------------------------------------------------===// 544 // Constructors and destructors. 545 546 ArchSpec::ArchSpec() = default; 547 548 ArchSpec::ArchSpec(const char *triple_cstr) { 549 if (triple_cstr) 550 SetTriple(triple_cstr); 551 } 552 553 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 554 555 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 556 557 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 558 SetArchitecture(arch_type, cpu, subtype); 559 } 560 561 ArchSpec::~ArchSpec() = default; 562 563 void ArchSpec::Clear() { 564 m_triple = llvm::Triple(); 565 m_core = kCore_invalid; 566 m_byte_order = eByteOrderInvalid; 567 m_flags = 0; 568 } 569 570 //===----------------------------------------------------------------------===// 571 // Predicates. 572 573 const char *ArchSpec::GetArchitectureName() const { 574 const CoreDefinition *core_def = FindCoreDefinition(m_core); 575 if (core_def) 576 return core_def->name; 577 return "unknown"; 578 } 579 580 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); } 581 582 std::string ArchSpec::GetTargetABI() const { 583 584 std::string abi; 585 586 if (IsMIPS()) { 587 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 588 case ArchSpec::eMIPSABI_N64: 589 abi = "n64"; 590 return abi; 591 case ArchSpec::eMIPSABI_N32: 592 abi = "n32"; 593 return abi; 594 case ArchSpec::eMIPSABI_O32: 595 abi = "o32"; 596 return abi; 597 default: 598 return abi; 599 } 600 } 601 return abi; 602 } 603 604 void ArchSpec::SetFlags(const std::string &elf_abi) { 605 606 uint32_t flag = GetFlags(); 607 if (IsMIPS()) { 608 if (elf_abi == "n64") 609 flag |= ArchSpec::eMIPSABI_N64; 610 else if (elf_abi == "n32") 611 flag |= ArchSpec::eMIPSABI_N32; 612 else if (elf_abi == "o32") 613 flag |= ArchSpec::eMIPSABI_O32; 614 } 615 SetFlags(flag); 616 } 617 618 std::string ArchSpec::GetClangTargetCPU() const { 619 std::string cpu; 620 if (IsMIPS()) { 621 switch (m_core) { 622 case ArchSpec::eCore_mips32: 623 case ArchSpec::eCore_mips32el: 624 cpu = "mips32"; 625 break; 626 case ArchSpec::eCore_mips32r2: 627 case ArchSpec::eCore_mips32r2el: 628 cpu = "mips32r2"; 629 break; 630 case ArchSpec::eCore_mips32r3: 631 case ArchSpec::eCore_mips32r3el: 632 cpu = "mips32r3"; 633 break; 634 case ArchSpec::eCore_mips32r5: 635 case ArchSpec::eCore_mips32r5el: 636 cpu = "mips32r5"; 637 break; 638 case ArchSpec::eCore_mips32r6: 639 case ArchSpec::eCore_mips32r6el: 640 cpu = "mips32r6"; 641 break; 642 case ArchSpec::eCore_mips64: 643 case ArchSpec::eCore_mips64el: 644 cpu = "mips64"; 645 break; 646 case ArchSpec::eCore_mips64r2: 647 case ArchSpec::eCore_mips64r2el: 648 cpu = "mips64r2"; 649 break; 650 case ArchSpec::eCore_mips64r3: 651 case ArchSpec::eCore_mips64r3el: 652 cpu = "mips64r3"; 653 break; 654 case ArchSpec::eCore_mips64r5: 655 case ArchSpec::eCore_mips64r5el: 656 cpu = "mips64r5"; 657 break; 658 case ArchSpec::eCore_mips64r6: 659 case ArchSpec::eCore_mips64r6el: 660 cpu = "mips64r6"; 661 break; 662 default: 663 break; 664 } 665 } 666 667 if (GetTriple().isARM()) 668 cpu = llvm::ARM::getARMCPUForArch(GetTriple(), "").str(); 669 return cpu; 670 } 671 672 uint32_t ArchSpec::GetMachOCPUType() const { 673 const CoreDefinition *core_def = FindCoreDefinition(m_core); 674 if (core_def) { 675 const ArchDefinitionEntry *arch_def = 676 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 677 if (arch_def) { 678 return arch_def->cpu; 679 } 680 } 681 return LLDB_INVALID_CPUTYPE; 682 } 683 684 uint32_t ArchSpec::GetMachOCPUSubType() const { 685 const CoreDefinition *core_def = FindCoreDefinition(m_core); 686 if (core_def) { 687 const ArchDefinitionEntry *arch_def = 688 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 689 if (arch_def) { 690 return arch_def->sub; 691 } 692 } 693 return LLDB_INVALID_CPUTYPE; 694 } 695 696 uint32_t ArchSpec::GetDataByteSize() const { 697 return 1; 698 } 699 700 uint32_t ArchSpec::GetCodeByteSize() const { 701 return 1; 702 } 703 704 llvm::Triple::ArchType ArchSpec::GetMachine() const { 705 const CoreDefinition *core_def = FindCoreDefinition(m_core); 706 if (core_def) 707 return core_def->machine; 708 709 return llvm::Triple::UnknownArch; 710 } 711 712 uint32_t ArchSpec::GetAddressByteSize() const { 713 const CoreDefinition *core_def = FindCoreDefinition(m_core); 714 if (core_def) { 715 if (core_def->machine == llvm::Triple::mips64 || 716 core_def->machine == llvm::Triple::mips64el) { 717 // For N32/O32 applications Address size is 4 bytes. 718 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 719 return 4; 720 } 721 return core_def->addr_byte_size; 722 } 723 return 0; 724 } 725 726 ByteOrder ArchSpec::GetDefaultEndian() const { 727 const CoreDefinition *core_def = FindCoreDefinition(m_core); 728 if (core_def) 729 return core_def->default_byte_order; 730 return eByteOrderInvalid; 731 } 732 733 bool ArchSpec::CharIsSignedByDefault() const { 734 switch (m_triple.getArch()) { 735 default: 736 return true; 737 738 case llvm::Triple::aarch64: 739 case llvm::Triple::aarch64_32: 740 case llvm::Triple::aarch64_be: 741 case llvm::Triple::arm: 742 case llvm::Triple::armeb: 743 case llvm::Triple::thumb: 744 case llvm::Triple::thumbeb: 745 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 746 747 case llvm::Triple::ppc: 748 case llvm::Triple::ppc64: 749 return m_triple.isOSDarwin(); 750 751 case llvm::Triple::ppc64le: 752 case llvm::Triple::systemz: 753 case llvm::Triple::xcore: 754 case llvm::Triple::arc: 755 return false; 756 } 757 } 758 759 lldb::ByteOrder ArchSpec::GetByteOrder() const { 760 if (m_byte_order == eByteOrderInvalid) 761 return GetDefaultEndian(); 762 return m_byte_order; 763 } 764 765 //===----------------------------------------------------------------------===// 766 // Mutators. 767 768 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 769 m_triple = triple; 770 UpdateCore(); 771 return IsValid(); 772 } 773 774 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 775 ArchSpec &arch) { 776 // Accept "12-10" or "12.10" as cpu type/subtype 777 if (triple_str.empty()) 778 return false; 779 780 size_t pos = triple_str.find_first_of("-."); 781 if (pos == llvm::StringRef::npos) 782 return false; 783 784 llvm::StringRef cpu_str = triple_str.substr(0, pos); 785 llvm::StringRef remainder = triple_str.substr(pos + 1); 786 if (cpu_str.empty() || remainder.empty()) 787 return false; 788 789 llvm::StringRef sub_str; 790 llvm::StringRef vendor; 791 llvm::StringRef os; 792 std::tie(sub_str, remainder) = remainder.split('-'); 793 std::tie(vendor, os) = remainder.split('-'); 794 795 uint32_t cpu = 0; 796 uint32_t sub = 0; 797 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 798 return false; 799 800 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 801 return false; 802 if (!vendor.empty() && !os.empty()) { 803 arch.GetTriple().setVendorName(vendor); 804 arch.GetTriple().setOSName(os); 805 } 806 807 return true; 808 } 809 810 bool ArchSpec::SetTriple(llvm::StringRef triple) { 811 if (triple.empty()) { 812 Clear(); 813 return false; 814 } 815 816 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 817 return true; 818 819 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 820 return IsValid(); 821 } 822 823 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 824 return !normalized_triple.getArchName().empty() && 825 normalized_triple.getOSName().empty() && 826 normalized_triple.getVendorName().empty() && 827 normalized_triple.getEnvironmentName().empty(); 828 } 829 830 void ArchSpec::MergeFrom(const ArchSpec &other) { 831 // ios-macabi always wins over macosx. 832 if ((GetTriple().getOS() == llvm::Triple::MacOSX || 833 GetTriple().getOS() == llvm::Triple::UnknownOS) && 834 other.GetTriple().getOS() == llvm::Triple::IOS && 835 other.GetTriple().getEnvironment() == llvm::Triple::MacABI) { 836 (*this) = other; 837 return; 838 } 839 840 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified()) 841 GetTriple().setVendor(other.GetTriple().getVendor()); 842 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified()) 843 GetTriple().setOS(other.GetTriple().getOS()); 844 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 845 GetTriple().setArch(other.GetTriple().getArch()); 846 847 // MachO unknown64 isn't really invalid as the debugger can still obtain 848 // information from the binary, e.g. line tables. As such, we don't update 849 // the core here. 850 if (other.GetCore() != eCore_uknownMach64) 851 UpdateCore(); 852 } 853 if (!TripleEnvironmentWasSpecified() && 854 other.TripleEnvironmentWasSpecified()) { 855 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 856 } 857 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 858 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 859 // adopt the specific arm core. 860 if (GetTriple().getArch() == llvm::Triple::arm && 861 other.GetTriple().getArch() == llvm::Triple::arm && 862 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 863 other.GetCore() != ArchSpec::eCore_arm_generic) { 864 m_core = other.GetCore(); 865 CoreUpdated(false); 866 } 867 if (GetFlags() == 0) { 868 SetFlags(other.GetFlags()); 869 } 870 } 871 872 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 873 uint32_t sub, uint32_t os) { 874 m_core = kCore_invalid; 875 bool update_triple = true; 876 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 877 if (arch_def) { 878 const ArchDefinitionEntry *arch_def_entry = 879 FindArchDefinitionEntry(arch_def, cpu, sub); 880 if (arch_def_entry) { 881 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 882 if (core_def) { 883 m_core = core_def->core; 884 update_triple = false; 885 // Always use the architecture name because it might be more 886 // descriptive than the architecture enum ("armv7" -> 887 // llvm::Triple::arm). 888 m_triple.setArchName(llvm::StringRef(core_def->name)); 889 if (arch_type == eArchTypeMachO) { 890 m_triple.setVendor(llvm::Triple::Apple); 891 892 // Don't set the OS. It could be simulator, macosx, ios, watchos, 893 // tvos, bridgeos. We could get close with the cpu type - but we 894 // can't get it right all of the time. Better to leave this unset 895 // so other sections of code will set it when they have more 896 // information. NB: don't call m_triple.setOS 897 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and 898 // the ArchSpec::TripleVendorWasSpecified() method says that any 899 // OSName setting means it was specified. 900 } else if (arch_type == eArchTypeELF) { 901 switch (os) { 902 case llvm::ELF::ELFOSABI_AIX: 903 m_triple.setOS(llvm::Triple::OSType::AIX); 904 break; 905 case llvm::ELF::ELFOSABI_FREEBSD: 906 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 907 break; 908 case llvm::ELF::ELFOSABI_GNU: 909 m_triple.setOS(llvm::Triple::OSType::Linux); 910 break; 911 case llvm::ELF::ELFOSABI_NETBSD: 912 m_triple.setOS(llvm::Triple::OSType::NetBSD); 913 break; 914 case llvm::ELF::ELFOSABI_OPENBSD: 915 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 916 break; 917 case llvm::ELF::ELFOSABI_SOLARIS: 918 m_triple.setOS(llvm::Triple::OSType::Solaris); 919 break; 920 case llvm::ELF::ELFOSABI_STANDALONE: 921 m_triple.setOS(llvm::Triple::OSType::UnknownOS); 922 break; 923 } 924 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 925 m_triple.setVendor(llvm::Triple::PC); 926 m_triple.setOS(llvm::Triple::Win32); 927 } else if (arch_type == eArchTypeXCOFF && os == llvm::Triple::AIX) { 928 m_triple.setVendor(llvm::Triple::IBM); 929 m_triple.setOS(llvm::Triple::AIX); 930 } else { 931 m_triple.setVendor(llvm::Triple::UnknownVendor); 932 m_triple.setOS(llvm::Triple::UnknownOS); 933 } 934 // Fall back onto setting the machine type if the arch by name 935 // failed... 936 if (m_triple.getArch() == llvm::Triple::UnknownArch) 937 m_triple.setArch(core_def->machine); 938 } 939 } else { 940 Log *log(GetLog(LLDBLog::Target | LLDBLog::Process | LLDBLog::Platform)); 941 LLDB_LOGF(log, 942 "Unable to find a core definition for cpu 0x%" PRIx32 943 " sub %" PRId32, 944 cpu, sub); 945 } 946 } 947 CoreUpdated(update_triple); 948 return IsValid(); 949 } 950 951 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 952 const CoreDefinition *core_def = FindCoreDefinition(m_core); 953 if (core_def) 954 return core_def->min_opcode_byte_size; 955 return 0; 956 } 957 958 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 959 const CoreDefinition *core_def = FindCoreDefinition(m_core); 960 if (core_def) 961 return core_def->max_opcode_byte_size; 962 return 0; 963 } 964 965 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 966 llvm::Triple::EnvironmentType rhs) { 967 if (lhs == rhs) 968 return true; 969 970 // Apple simulators are a different platform than what they simulate. 971 // As the environments are different at this point, if one of them is a 972 // simulator, then they are different. 973 if (lhs == llvm::Triple::Simulator || rhs == llvm::Triple::Simulator) 974 return false; 975 976 // If any of the environment is unknown then they are compatible 977 if (lhs == llvm::Triple::UnknownEnvironment || 978 rhs == llvm::Triple::UnknownEnvironment) 979 return true; 980 981 // If one of the environment is Android and the other one is EABI then they 982 // are considered to be compatible. This is required as a workaround for 983 // shared libraries compiled for Android without the NOTE section indicating 984 // that they are using the Android ABI. 985 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 986 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 987 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 988 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 989 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 990 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 991 return true; 992 993 return false; 994 } 995 996 bool ArchSpec::IsMatch(const ArchSpec &rhs, MatchType match) const { 997 if (GetByteOrder() != rhs.GetByteOrder() || 998 !cores_match(GetCore(), rhs.GetCore(), true, match == ExactMatch)) 999 return false; 1000 1001 const llvm::Triple &lhs_triple = GetTriple(); 1002 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1003 1004 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1005 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1006 1007 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1008 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1009 1010 bool both_windows = lhs_triple.isOSWindows() && rhs_triple.isOSWindows(); 1011 1012 // On Windows, the vendor field doesn't have any practical effect, but 1013 // it is often set to either "pc" or "w64". 1014 if ((lhs_triple_vendor != rhs_triple_vendor) && 1015 (match == ExactMatch || !both_windows)) { 1016 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1017 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1018 // Both architectures had the vendor specified, so if they aren't equal 1019 // then we return false 1020 if (rhs_vendor_specified && lhs_vendor_specified) 1021 return false; 1022 1023 // Only fail if both vendor types are not unknown 1024 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1025 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1026 return false; 1027 } 1028 1029 const llvm::Triple::EnvironmentType lhs_triple_env = 1030 lhs_triple.getEnvironment(); 1031 const llvm::Triple::EnvironmentType rhs_triple_env = 1032 rhs_triple.getEnvironment(); 1033 1034 if (match == CompatibleMatch) { 1035 // x86_64-apple-ios-macabi, x86_64-apple-macosx are compatible, no match. 1036 if ((lhs_triple_os == llvm::Triple::IOS && 1037 lhs_triple_env == llvm::Triple::MacABI && 1038 rhs_triple_os == llvm::Triple::MacOSX) || 1039 (lhs_triple_os == llvm::Triple::MacOSX && 1040 rhs_triple_os == llvm::Triple::IOS && 1041 rhs_triple_env == llvm::Triple::MacABI)) 1042 return true; 1043 } 1044 1045 // x86_64-apple-ios-macabi and x86_64-apple-ios are not compatible. 1046 if (lhs_triple_os == llvm::Triple::IOS && 1047 rhs_triple_os == llvm::Triple::IOS && 1048 (lhs_triple_env == llvm::Triple::MacABI || 1049 rhs_triple_env == llvm::Triple::MacABI) && 1050 lhs_triple_env != rhs_triple_env) 1051 return false; 1052 1053 if (lhs_triple_os != rhs_triple_os) { 1054 const bool lhs_os_specified = TripleOSWasSpecified(); 1055 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1056 // If both OS types are specified and different, fail. 1057 if (lhs_os_specified && rhs_os_specified) 1058 return false; 1059 1060 // If the pair of os+env is both unspecified, match any other os+env combo. 1061 if (match == CompatibleMatch && 1062 ((!lhs_os_specified && !lhs_triple.hasEnvironment()) || 1063 (!rhs_os_specified && !rhs_triple.hasEnvironment()))) 1064 return true; 1065 } 1066 1067 if (match == CompatibleMatch && both_windows) 1068 return true; // The Windows environments (MSVC vs GNU) are compatible 1069 1070 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env); 1071 } 1072 1073 void ArchSpec::UpdateCore() { 1074 llvm::StringRef arch_name(m_triple.getArchName()); 1075 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1076 if (core_def) { 1077 m_core = core_def->core; 1078 // Set the byte order to the default byte order for an architecture. This 1079 // can be modified if needed for cases when cores handle both big and 1080 // little endian 1081 m_byte_order = core_def->default_byte_order; 1082 } else { 1083 Clear(); 1084 } 1085 } 1086 1087 //===----------------------------------------------------------------------===// 1088 // Helper methods. 1089 1090 void ArchSpec::CoreUpdated(bool update_triple) { 1091 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1092 if (core_def) { 1093 if (update_triple) 1094 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1095 m_byte_order = core_def->default_byte_order; 1096 } else { 1097 if (update_triple) 1098 m_triple = llvm::Triple(); 1099 m_byte_order = eByteOrderInvalid; 1100 } 1101 } 1102 1103 //===----------------------------------------------------------------------===// 1104 // Operators. 1105 1106 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1107 bool try_inverse, bool enforce_exact_match) { 1108 if (core1 == core2) 1109 return true; 1110 1111 switch (core1) { 1112 case ArchSpec::kCore_any: 1113 return true; 1114 1115 case ArchSpec::eCore_arm_generic: 1116 if (enforce_exact_match) 1117 break; 1118 [[fallthrough]]; 1119 case ArchSpec::kCore_arm_any: 1120 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1121 return true; 1122 if (core2 >= ArchSpec::kCore_thumb_first && 1123 core2 <= ArchSpec::kCore_thumb_last) 1124 return true; 1125 if (core2 == ArchSpec::kCore_arm_any) 1126 return true; 1127 break; 1128 1129 case ArchSpec::kCore_x86_32_any: 1130 if ((core2 >= ArchSpec::kCore_x86_32_first && 1131 core2 <= ArchSpec::kCore_x86_32_last) || 1132 (core2 == ArchSpec::kCore_x86_32_any)) 1133 return true; 1134 break; 1135 1136 case ArchSpec::kCore_x86_64_any: 1137 if ((core2 >= ArchSpec::kCore_x86_64_first && 1138 core2 <= ArchSpec::kCore_x86_64_last) || 1139 (core2 == ArchSpec::kCore_x86_64_any)) 1140 return true; 1141 break; 1142 1143 case ArchSpec::kCore_ppc_any: 1144 if ((core2 >= ArchSpec::kCore_ppc_first && 1145 core2 <= ArchSpec::kCore_ppc_last) || 1146 (core2 == ArchSpec::kCore_ppc_any)) 1147 return true; 1148 break; 1149 1150 case ArchSpec::kCore_ppc64_any: 1151 if ((core2 >= ArchSpec::kCore_ppc64_first && 1152 core2 <= ArchSpec::kCore_ppc64_last) || 1153 (core2 == ArchSpec::kCore_ppc64_any)) 1154 return true; 1155 break; 1156 1157 case ArchSpec::kCore_hexagon_any: 1158 if ((core2 >= ArchSpec::kCore_hexagon_first && 1159 core2 <= ArchSpec::kCore_hexagon_last) || 1160 (core2 == ArchSpec::kCore_hexagon_any)) 1161 return true; 1162 break; 1163 1164 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1165 // Cortex-M0 - ARMv6-M - armv6m 1166 // Cortex-M3 - ARMv7-M - armv7m 1167 // Cortex-M4 - ARMv7E-M - armv7em 1168 case ArchSpec::eCore_arm_armv7em: 1169 if (!enforce_exact_match) { 1170 if (core2 == ArchSpec::eCore_arm_generic) 1171 return true; 1172 if (core2 == ArchSpec::eCore_arm_armv7m) 1173 return true; 1174 if (core2 == ArchSpec::eCore_arm_armv6m) 1175 return true; 1176 if (core2 == ArchSpec::eCore_arm_armv7) 1177 return true; 1178 try_inverse = true; 1179 } 1180 break; 1181 1182 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1183 // Cortex-M0 - ARMv6-M - armv6m 1184 // Cortex-M3 - ARMv7-M - armv7m 1185 // Cortex-M4 - ARMv7E-M - armv7em 1186 case ArchSpec::eCore_arm_armv7m: 1187 if (!enforce_exact_match) { 1188 if (core2 == ArchSpec::eCore_arm_generic) 1189 return true; 1190 if (core2 == ArchSpec::eCore_arm_armv6m) 1191 return true; 1192 if (core2 == ArchSpec::eCore_arm_armv7) 1193 return true; 1194 if (core2 == ArchSpec::eCore_arm_armv7em) 1195 return true; 1196 try_inverse = true; 1197 } 1198 break; 1199 1200 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1201 // Cortex-M0 - ARMv6-M - armv6m 1202 // Cortex-M3 - ARMv7-M - armv7m 1203 // Cortex-M4 - ARMv7E-M - armv7em 1204 case ArchSpec::eCore_arm_armv6m: 1205 if (!enforce_exact_match) { 1206 if (core2 == ArchSpec::eCore_arm_generic) 1207 return true; 1208 if (core2 == ArchSpec::eCore_arm_armv7em) 1209 return true; 1210 if (core2 == ArchSpec::eCore_arm_armv7) 1211 return true; 1212 if (core2 == ArchSpec::eCore_arm_armv6m) 1213 return true; 1214 try_inverse = false; 1215 } 1216 break; 1217 1218 case ArchSpec::eCore_arm_armv7f: 1219 case ArchSpec::eCore_arm_armv7k: 1220 case ArchSpec::eCore_arm_armv7s: 1221 case ArchSpec::eCore_arm_armv7l: 1222 case ArchSpec::eCore_arm_armv8l: 1223 if (!enforce_exact_match) { 1224 if (core2 == ArchSpec::eCore_arm_generic) 1225 return true; 1226 if (core2 == ArchSpec::eCore_arm_armv7) 1227 return true; 1228 try_inverse = false; 1229 } 1230 break; 1231 1232 case ArchSpec::eCore_x86_64_x86_64h: 1233 case ArchSpec::eCore_x86_64_amd64: 1234 if (!enforce_exact_match) { 1235 try_inverse = false; 1236 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1237 return true; 1238 } 1239 break; 1240 1241 case ArchSpec::eCore_arm_armv8: 1242 if (!enforce_exact_match) { 1243 if (core2 == ArchSpec::eCore_arm_arm64) 1244 return true; 1245 if (core2 == ArchSpec::eCore_arm_aarch64) 1246 return true; 1247 if (core2 == ArchSpec::eCore_arm_arm64e) 1248 return true; 1249 try_inverse = false; 1250 } 1251 break; 1252 1253 case ArchSpec::eCore_arm_arm64e: 1254 if (!enforce_exact_match) { 1255 if (core2 == ArchSpec::eCore_arm_arm64) 1256 return true; 1257 if (core2 == ArchSpec::eCore_arm_aarch64) 1258 return true; 1259 if (core2 == ArchSpec::eCore_arm_armv8) 1260 return true; 1261 try_inverse = false; 1262 } 1263 break; 1264 case ArchSpec::eCore_arm_aarch64: 1265 if (!enforce_exact_match) { 1266 if (core2 == ArchSpec::eCore_arm_arm64) 1267 return true; 1268 if (core2 == ArchSpec::eCore_arm_armv8) 1269 return true; 1270 if (core2 == ArchSpec::eCore_arm_arm64e) 1271 return true; 1272 try_inverse = false; 1273 } 1274 break; 1275 1276 case ArchSpec::eCore_arm_arm64: 1277 if (!enforce_exact_match) { 1278 if (core2 == ArchSpec::eCore_arm_aarch64) 1279 return true; 1280 if (core2 == ArchSpec::eCore_arm_armv8) 1281 return true; 1282 if (core2 == ArchSpec::eCore_arm_arm64e) 1283 return true; 1284 try_inverse = false; 1285 } 1286 break; 1287 1288 case ArchSpec::eCore_arm_arm64_32: 1289 if (!enforce_exact_match) { 1290 if (core2 == ArchSpec::eCore_arm_generic) 1291 return true; 1292 try_inverse = false; 1293 } 1294 break; 1295 1296 case ArchSpec::eCore_mips32: 1297 if (!enforce_exact_match) { 1298 if (core2 >= ArchSpec::kCore_mips32_first && 1299 core2 <= ArchSpec::kCore_mips32_last) 1300 return true; 1301 try_inverse = false; 1302 } 1303 break; 1304 1305 case ArchSpec::eCore_mips32el: 1306 if (!enforce_exact_match) { 1307 if (core2 >= ArchSpec::kCore_mips32el_first && 1308 core2 <= ArchSpec::kCore_mips32el_last) 1309 return true; 1310 try_inverse = true; 1311 } 1312 break; 1313 1314 case ArchSpec::eCore_mips64: 1315 if (!enforce_exact_match) { 1316 if (core2 >= ArchSpec::kCore_mips32_first && 1317 core2 <= ArchSpec::kCore_mips32_last) 1318 return true; 1319 if (core2 >= ArchSpec::kCore_mips64_first && 1320 core2 <= ArchSpec::kCore_mips64_last) 1321 return true; 1322 try_inverse = false; 1323 } 1324 break; 1325 1326 case ArchSpec::eCore_mips64el: 1327 if (!enforce_exact_match) { 1328 if (core2 >= ArchSpec::kCore_mips32el_first && 1329 core2 <= ArchSpec::kCore_mips32el_last) 1330 return true; 1331 if (core2 >= ArchSpec::kCore_mips64el_first && 1332 core2 <= ArchSpec::kCore_mips64el_last) 1333 return true; 1334 try_inverse = false; 1335 } 1336 break; 1337 1338 case ArchSpec::eCore_mips64r2: 1339 case ArchSpec::eCore_mips64r3: 1340 case ArchSpec::eCore_mips64r5: 1341 if (!enforce_exact_match) { 1342 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1343 return true; 1344 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1345 return true; 1346 try_inverse = false; 1347 } 1348 break; 1349 1350 case ArchSpec::eCore_mips64r2el: 1351 case ArchSpec::eCore_mips64r3el: 1352 case ArchSpec::eCore_mips64r5el: 1353 if (!enforce_exact_match) { 1354 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1355 return true; 1356 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1357 return true; 1358 try_inverse = false; 1359 } 1360 break; 1361 1362 case ArchSpec::eCore_mips32r2: 1363 case ArchSpec::eCore_mips32r3: 1364 case ArchSpec::eCore_mips32r5: 1365 if (!enforce_exact_match) { 1366 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1367 return true; 1368 } 1369 break; 1370 1371 case ArchSpec::eCore_mips32r2el: 1372 case ArchSpec::eCore_mips32r3el: 1373 case ArchSpec::eCore_mips32r5el: 1374 if (!enforce_exact_match) { 1375 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1376 return true; 1377 } 1378 break; 1379 1380 case ArchSpec::eCore_mips32r6: 1381 if (!enforce_exact_match) { 1382 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1383 return true; 1384 } 1385 break; 1386 1387 case ArchSpec::eCore_mips32r6el: 1388 if (!enforce_exact_match) { 1389 if (core2 == ArchSpec::eCore_mips32el || 1390 core2 == ArchSpec::eCore_mips32r6el) 1391 return true; 1392 } 1393 break; 1394 1395 case ArchSpec::eCore_mips64r6: 1396 if (!enforce_exact_match) { 1397 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1398 return true; 1399 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1400 return true; 1401 } 1402 break; 1403 1404 case ArchSpec::eCore_mips64r6el: 1405 if (!enforce_exact_match) { 1406 if (core2 == ArchSpec::eCore_mips32el || 1407 core2 == ArchSpec::eCore_mips32r6el) 1408 return true; 1409 if (core2 == ArchSpec::eCore_mips64el || 1410 core2 == ArchSpec::eCore_mips64r6el) 1411 return true; 1412 } 1413 break; 1414 1415 default: 1416 break; 1417 } 1418 if (try_inverse) 1419 return cores_match(core2, core1, false, enforce_exact_match); 1420 return false; 1421 } 1422 1423 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1424 const ArchSpec::Core lhs_core = lhs.GetCore(); 1425 const ArchSpec::Core rhs_core = rhs.GetCore(); 1426 return lhs_core < rhs_core; 1427 } 1428 1429 1430 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1431 return lhs.GetCore() == rhs.GetCore(); 1432 } 1433 1434 bool ArchSpec::IsFullySpecifiedTriple() const { 1435 if (!TripleOSWasSpecified()) 1436 return false; 1437 1438 if (!TripleVendorWasSpecified()) 1439 return false; 1440 1441 const unsigned unspecified = 0; 1442 const llvm::Triple &triple = GetTriple(); 1443 if (triple.isOSDarwin() && triple.getOSMajorVersion() == unspecified) 1444 return false; 1445 1446 return true; 1447 } 1448 1449 bool ArchSpec::IsAlwaysThumbInstructions() const { 1450 std::string Status; 1451 if (GetTriple().getArch() == llvm::Triple::arm || 1452 GetTriple().getArch() == llvm::Triple::thumb) { 1453 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1454 // 1455 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1456 // execute thumb instructions. We map the cores to arch names like this: 1457 // 1458 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1459 // Cortex-M7: armv7em 1460 1461 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1462 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1463 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1464 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1465 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1466 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1467 return true; 1468 } 1469 // Windows on ARM is always thumb. 1470 if (GetTriple().isOSWindows()) 1471 return true; 1472 } 1473 return false; 1474 } 1475 1476 void ArchSpec::DumpTriple(llvm::raw_ostream &s) const { 1477 const llvm::Triple &triple = GetTriple(); 1478 llvm::StringRef arch_str = triple.getArchName(); 1479 llvm::StringRef vendor_str = triple.getVendorName(); 1480 llvm::StringRef os_str = triple.getOSName(); 1481 llvm::StringRef environ_str = triple.getEnvironmentName(); 1482 1483 s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str, 1484 vendor_str.empty() ? "*" : vendor_str, 1485 os_str.empty() ? "*" : os_str); 1486 1487 if (!environ_str.empty()) 1488 s << "-" << environ_str; 1489 } 1490